603 lines
19 KiB
Rust
603 lines
19 KiB
Rust
#![macro_use]
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//! Provide access to the STM32 digital-to-analog converter (DAC).
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use core::marker::PhantomData;
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use embassy_hal_internal::{into_ref, PeripheralRef};
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use crate::pac::dac;
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use crate::rcc::RccPeripheral;
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use crate::{peripherals, Peripheral};
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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/// Custom Errors
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pub enum Error {
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UnconfiguredChannel,
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InvalidValue,
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}
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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/// DAC Channels
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pub enum Channel {
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Ch1,
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Ch2,
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}
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impl Channel {
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const fn index(&self) -> usize {
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match self {
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Channel::Ch1 => 0,
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Channel::Ch2 => 1,
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}
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}
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}
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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/// Trigger sources for CH1
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pub enum Ch1Trigger {
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#[cfg(dac_v3)]
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Tim1,
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Tim2,
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#[cfg(not(dac_v3))]
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Tim3,
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#[cfg(dac_v3)]
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Tim4,
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#[cfg(dac_v3)]
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Tim5,
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Tim6,
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Tim7,
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#[cfg(dac_v3)]
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Tim8,
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Tim15,
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#[cfg(dac_v3)]
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Hrtim1Dactrg1,
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#[cfg(dac_v3)]
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Hrtim1Dactrg2,
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#[cfg(dac_v3)]
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Lptim1,
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#[cfg(dac_v3)]
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Lptim2,
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#[cfg(dac_v3)]
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Lptim3,
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Exti9,
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Software,
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}
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impl Ch1Trigger {
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fn tsel(&self) -> dac::vals::Tsel1 {
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match self {
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#[cfg(dac_v3)]
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Ch1Trigger::Tim1 => dac::vals::Tsel1::TIM1_TRGO,
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Ch1Trigger::Tim2 => dac::vals::Tsel1::TIM2_TRGO,
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#[cfg(not(dac_v3))]
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Ch1Trigger::Tim3 => dac::vals::Tsel1::TIM3_TRGO,
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#[cfg(dac_v3)]
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Ch1Trigger::Tim4 => dac::vals::Tsel1::TIM4_TRGO,
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#[cfg(dac_v3)]
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Ch1Trigger::Tim5 => dac::vals::Tsel1::TIM5_TRGO,
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Ch1Trigger::Tim6 => dac::vals::Tsel1::TIM6_TRGO,
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Ch1Trigger::Tim7 => dac::vals::Tsel1::TIM7_TRGO,
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#[cfg(dac_v3)]
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Ch1Trigger::Tim8 => dac::vals::Tsel1::TIM8_TRGO,
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Ch1Trigger::Tim15 => dac::vals::Tsel1::TIM15_TRGO,
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#[cfg(dac_v3)]
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Ch1Trigger::Hrtim1Dactrg1 => dac::vals::Tsel1::HRTIM1_DACTRG1,
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#[cfg(dac_v3)]
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Ch1Trigger::Hrtim1Dactrg2 => dac::vals::Tsel1::HRTIM1_DACTRG2,
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#[cfg(dac_v3)]
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Ch1Trigger::Lptim1 => dac::vals::Tsel1::LPTIM1_OUT,
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#[cfg(dac_v3)]
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Ch1Trigger::Lptim2 => dac::vals::Tsel1::LPTIM2_OUT,
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#[cfg(dac_v3)]
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Ch1Trigger::Lptim3 => dac::vals::Tsel1::LPTIM3_OUT,
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Ch1Trigger::Exti9 => dac::vals::Tsel1::EXTI9,
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Ch1Trigger::Software => dac::vals::Tsel1::SOFTWARE,
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}
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}
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}
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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/// Trigger sources for CH2
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pub enum Ch2Trigger {
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Tim6,
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Tim8,
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Tim7,
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Tim5,
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Tim2,
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Tim4,
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Exti9,
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Software,
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}
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impl Ch2Trigger {
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fn tsel(&self) -> dac::vals::Tsel2 {
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match self {
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Ch2Trigger::Tim6 => dac::vals::Tsel2::TIM6_TRGO,
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Ch2Trigger::Tim8 => dac::vals::Tsel2::TIM8_TRGO,
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Ch2Trigger::Tim7 => dac::vals::Tsel2::TIM7_TRGO,
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Ch2Trigger::Tim5 => dac::vals::Tsel2::TIM5_TRGO,
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Ch2Trigger::Tim2 => dac::vals::Tsel2::TIM2_TRGO,
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Ch2Trigger::Tim4 => dac::vals::Tsel2::TIM4_TRGO,
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Ch2Trigger::Exti9 => dac::vals::Tsel2::EXTI9,
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Ch2Trigger::Software => dac::vals::Tsel2::SOFTWARE,
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}
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}
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}
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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/// Single 8 or 12 bit value that can be output by the DAC
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pub enum Value {
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// 8 bit value
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Bit8(u8),
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// 12 bit value stored in a u16, left-aligned
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Bit12Left(u16),
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// 12 bit value stored in a u16, right-aligned
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Bit12Right(u16),
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}
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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/// Array variant of [`Value`]
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pub enum ValueArray<'a> {
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// 8 bit values
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Bit8(&'a [u8]),
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// 12 bit value stored in a u16, left-aligned
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Bit12Left(&'a [u16]),
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// 12 bit values stored in a u16, right-aligned
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Bit12Right(&'a [u16]),
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}
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/// Provide common functions for DAC channels
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pub trait DacChannel<T: Instance, Tx> {
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const CHANNEL: Channel;
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/// Enable trigger of the given channel
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fn set_trigger_enable(&mut self, on: bool) -> Result<(), Error> {
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T::regs().cr().modify(|reg| {
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reg.set_ten(Self::CHANNEL.index(), on);
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});
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Ok(())
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}
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/// Set mode register of the given channel
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#[cfg(any(dac_v2, dac_v3))]
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fn set_channel_mode(&mut self, val: u8) -> Result<(), Error> {
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T::regs().mcr().modify(|reg| {
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reg.set_mode(Self::CHANNEL.index(), val);
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});
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Ok(())
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}
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/// Set enable register of the given channel
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fn set_channel_enable(&mut self, on: bool) -> Result<(), Error> {
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T::regs().cr().modify(|reg| {
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reg.set_en(Self::CHANNEL.index(), on);
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});
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Ok(())
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}
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/// Enable the DAC channel `ch`
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fn enable_channel(&mut self) -> Result<(), Error> {
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self.set_channel_enable(true)
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}
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/// Disable the DAC channel `ch`
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fn disable_channel(&mut self) -> Result<(), Error> {
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self.set_channel_enable(false)
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}
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/// Perform a software trigger on `ch`
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fn trigger(&mut self) {
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T::regs().swtrigr().write(|reg| {
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reg.set_swtrig(Self::CHANNEL.index(), true);
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});
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}
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/// Set a value to be output by the DAC on trigger.
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///
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/// The `value` is written to the corresponding "data holding register".
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fn set(&mut self, value: Value) -> Result<(), Error> {
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match value {
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Value::Bit8(v) => T::regs().dhr8r(Self::CHANNEL.index()).write(|reg| reg.set_dhr(v)),
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Value::Bit12Left(v) => T::regs().dhr12l(Self::CHANNEL.index()).write(|reg| reg.set_dhr(v)),
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Value::Bit12Right(v) => T::regs().dhr12r(Self::CHANNEL.index()).write(|reg| reg.set_dhr(v)),
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}
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Ok(())
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}
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}
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/// Hold two DAC channels
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///
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/// Note: This consumes the DAC `Instance` only once, allowing to get both channels simultaneously.
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///
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/// # Example for obtaining both DAC channels
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///
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/// ```ignore
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/// // DMA channels and pins may need to be changed for your controller
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/// let (dac_ch1, dac_ch2) =
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/// embassy_stm32::dac::Dac::new(p.DAC1, p.DMA1_CH3, p.DMA1_CH4, p.PA4, p.PA5).split();
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/// ```
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pub struct Dac<'d, T: Instance, TxCh1, TxCh2> {
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ch1: DacCh1<'d, T, TxCh1>,
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ch2: DacCh2<'d, T, TxCh2>,
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}
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/// DAC CH1
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///
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/// Note: This consumes the DAC `Instance`. Use [`Dac::new`] to get both channels simultaneously.
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pub struct DacCh1<'d, T: Instance, Tx> {
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/// To consume T
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_peri: PeripheralRef<'d, T>,
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#[allow(unused)] // For chips whose DMA is not (yet) supported
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dma: PeripheralRef<'d, Tx>,
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}
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/// DAC CH2
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///
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/// Note: This consumes the DAC `Instance`. Use [`Dac::new`] to get both channels simultaneously.
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pub struct DacCh2<'d, T: Instance, Tx> {
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/// Instead of PeripheralRef to consume T
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phantom: PhantomData<&'d mut T>,
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#[allow(unused)] // For chips whose DMA is not (yet) supported
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dma: PeripheralRef<'d, Tx>,
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}
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impl<'d, T: Instance, Tx> DacCh1<'d, T, Tx> {
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/// Obtain DAC CH1
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pub fn new(
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peri: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = Tx> + 'd,
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pin: impl Peripheral<P = impl DacPin<T, 1>> + crate::gpio::sealed::Pin + 'd,
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) -> Self {
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pin.set_as_analog();
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into_ref!(peri, dma);
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T::enable_and_reset();
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let mut dac = Self { _peri: peri, dma };
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// Configure each activated channel. All results can be `unwrap`ed since they
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// will only error if the channel is not configured (i.e. ch1, ch2 are false)
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#[cfg(any(dac_v2, dac_v3))]
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dac.set_channel_mode(0).unwrap();
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dac.enable_channel().unwrap();
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dac.set_trigger_enable(true).unwrap();
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dac
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}
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/// Select a new trigger for this channel
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///
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/// **Important**: This disables the channel!
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pub fn select_trigger(&mut self, trigger: Ch1Trigger) -> Result<(), Error> {
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unwrap!(self.disable_channel());
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T::regs().cr().modify(|reg| {
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reg.set_tsel1(trigger.tsel());
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});
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Ok(())
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}
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/// Write `data` to the DAC CH1 via DMA.
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///
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/// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
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/// This will configure a circular DMA transfer that periodically outputs the `data`.
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/// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
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///
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/// **Important:** Channel 1 has to be configured for the DAC instance!
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pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
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where
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Tx: DmaCh1<T>,
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{
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let channel = Channel::Ch1.index();
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debug!("Writing to channel {}", channel);
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// Enable DAC and DMA
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T::regs().cr().modify(|w| {
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w.set_en(channel, true);
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w.set_dmaen(channel, true);
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});
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let tx_request = self.dma.request();
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let dma_channel = &mut self.dma;
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let tx_options = crate::dma::TransferOptions {
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circular,
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half_transfer_ir: false,
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complete_transfer_ir: !circular,
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..Default::default()
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};
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// Initiate the correct type of DMA transfer depending on what data is passed
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let tx_f = match data {
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ValueArray::Bit8(buf) => unsafe {
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crate::dma::Transfer::new_write(
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dma_channel,
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tx_request,
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buf,
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T::regs().dhr8r(channel).as_ptr() as *mut u8,
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tx_options,
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)
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},
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ValueArray::Bit12Left(buf) => unsafe {
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crate::dma::Transfer::new_write(
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dma_channel,
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tx_request,
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buf,
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T::regs().dhr12l(channel).as_ptr() as *mut u16,
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tx_options,
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)
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},
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ValueArray::Bit12Right(buf) => unsafe {
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crate::dma::Transfer::new_write(
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dma_channel,
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tx_request,
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buf,
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T::regs().dhr12r(channel).as_ptr() as *mut u16,
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tx_options,
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)
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},
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};
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tx_f.await;
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// finish dma
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// TODO: Do we need to check any status registers here?
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T::regs().cr().modify(|w| {
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// Disable the DAC peripheral
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w.set_en(channel, false);
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// Disable the DMA. TODO: Is this necessary?
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w.set_dmaen(channel, false);
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});
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Ok(())
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}
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}
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impl<'d, T: Instance, Tx> DacCh2<'d, T, Tx> {
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/// Obtain DAC CH2
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pub fn new(
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_peri: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = Tx> + 'd,
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pin: impl Peripheral<P = impl DacPin<T, 2>> + crate::gpio::sealed::Pin + 'd,
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) -> Self {
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pin.set_as_analog();
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into_ref!(_peri, dma);
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T::enable_and_reset();
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let mut dac = Self {
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phantom: PhantomData,
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dma,
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};
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// Configure each activated channel. All results can be `unwrap`ed since they
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// will only error if the channel is not configured (i.e. ch1, ch2 are false)
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#[cfg(any(dac_v2, dac_v3))]
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dac.set_channel_mode(0).unwrap();
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dac.enable_channel().unwrap();
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dac.set_trigger_enable(true).unwrap();
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dac
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}
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/// Select a new trigger for this channel
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pub fn select_trigger(&mut self, trigger: Ch2Trigger) -> Result<(), Error> {
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unwrap!(self.disable_channel());
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T::regs().cr().modify(|reg| {
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reg.set_tsel2(trigger.tsel());
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});
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Ok(())
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}
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/// Write `data` to the DAC CH2 via DMA.
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///
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/// To prevent delays/glitches when outputting a periodic waveform, the `circular` flag can be set.
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/// This will configure a circular DMA transfer that periodically outputs the `data`.
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/// Note that for performance reasons in circular mode the transfer complete interrupt is disabled.
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///
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/// **Important:** Channel 2 has to be configured for the DAC instance!
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pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) -> Result<(), Error>
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where
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Tx: DmaCh2<T>,
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{
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let channel = Channel::Ch2.index();
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debug!("Writing to channel {}", channel);
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// Enable DAC and DMA
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T::regs().cr().modify(|w| {
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w.set_en(channel, true);
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w.set_dmaen(channel, true);
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});
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let tx_request = self.dma.request();
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let dma_channel = &mut self.dma;
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let tx_options = crate::dma::TransferOptions {
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circular,
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half_transfer_ir: false,
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complete_transfer_ir: !circular,
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..Default::default()
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};
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// Initiate the correct type of DMA transfer depending on what data is passed
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let tx_f = match data {
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ValueArray::Bit8(buf) => unsafe {
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crate::dma::Transfer::new_write(
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dma_channel,
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tx_request,
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buf,
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T::regs().dhr8r(channel).as_ptr() as *mut u8,
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tx_options,
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)
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},
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ValueArray::Bit12Left(buf) => unsafe {
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crate::dma::Transfer::new_write(
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dma_channel,
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tx_request,
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buf,
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T::regs().dhr12l(channel).as_ptr() as *mut u16,
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tx_options,
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)
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},
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ValueArray::Bit12Right(buf) => unsafe {
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crate::dma::Transfer::new_write(
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dma_channel,
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tx_request,
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buf,
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T::regs().dhr12r(channel).as_ptr() as *mut u16,
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tx_options,
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)
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},
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};
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tx_f.await;
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// finish dma
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// TODO: Do we need to check any status registers here?
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T::regs().cr().modify(|w| {
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// Disable the DAC peripheral
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w.set_en(channel, false);
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// Disable the DMA. TODO: Is this necessary?
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w.set_dmaen(channel, false);
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});
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Ok(())
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}
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}
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impl<'d, T: Instance, TxCh1, TxCh2> Dac<'d, T, TxCh1, TxCh2> {
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/// Create a new DAC instance with both channels.
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///
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/// This is used to obtain two independent channels via `split()` for use e.g. with DMA.
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pub fn new(
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peri: impl Peripheral<P = T> + 'd,
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dma_ch1: impl Peripheral<P = TxCh1> + 'd,
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dma_ch2: impl Peripheral<P = TxCh2> + 'd,
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pin_ch1: impl Peripheral<P = impl DacPin<T, 1>> + crate::gpio::sealed::Pin + 'd,
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pin_ch2: impl Peripheral<P = impl DacPin<T, 2>> + crate::gpio::sealed::Pin + 'd,
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) -> Self {
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pin_ch1.set_as_analog();
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pin_ch2.set_as_analog();
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into_ref!(peri, dma_ch1, dma_ch2);
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T::enable_and_reset();
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let mut dac_ch1 = DacCh1 {
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_peri: peri,
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dma: dma_ch1,
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};
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let mut dac_ch2 = DacCh2 {
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phantom: PhantomData,
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dma: dma_ch2,
|
|
};
|
|
|
|
// Configure each activated channel. All results can be `unwrap`ed since they
|
|
// will only error if the channel is not configured (i.e. ch1, ch2 are false)
|
|
#[cfg(any(dac_v2, dac_v3))]
|
|
dac_ch1.set_channel_mode(0).unwrap();
|
|
dac_ch1.enable_channel().unwrap();
|
|
dac_ch1.set_trigger_enable(true).unwrap();
|
|
|
|
#[cfg(any(dac_v2, dac_v3))]
|
|
dac_ch2.set_channel_mode(0).unwrap();
|
|
dac_ch2.enable_channel().unwrap();
|
|
dac_ch2.set_trigger_enable(true).unwrap();
|
|
|
|
Self {
|
|
ch1: dac_ch1,
|
|
ch2: dac_ch2,
|
|
}
|
|
}
|
|
|
|
/// Split the DAC into CH1 and CH2 for independent use.
|
|
pub fn split(self) -> (DacCh1<'d, T, TxCh1>, DacCh2<'d, T, TxCh2>) {
|
|
(self.ch1, self.ch2)
|
|
}
|
|
|
|
/// Get mutable reference to CH1
|
|
pub fn ch1_mut(&mut self) -> &mut DacCh1<'d, T, TxCh1> {
|
|
&mut self.ch1
|
|
}
|
|
|
|
/// Get mutable reference to CH2
|
|
pub fn ch2_mut(&mut self) -> &mut DacCh2<'d, T, TxCh2> {
|
|
&mut self.ch2
|
|
}
|
|
|
|
/// Get reference to CH1
|
|
pub fn ch1(&mut self) -> &DacCh1<'d, T, TxCh1> {
|
|
&self.ch1
|
|
}
|
|
|
|
/// Get reference to CH2
|
|
pub fn ch2(&mut self) -> &DacCh2<'d, T, TxCh2> {
|
|
&self.ch2
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance, Tx> DacChannel<T, Tx> for DacCh1<'d, T, Tx> {
|
|
const CHANNEL: Channel = Channel::Ch1;
|
|
}
|
|
|
|
impl<'d, T: Instance, Tx> DacChannel<T, Tx> for DacCh2<'d, T, Tx> {
|
|
const CHANNEL: Channel = Channel::Ch2;
|
|
}
|
|
|
|
pub(crate) mod sealed {
|
|
pub trait Instance {
|
|
fn regs() -> &'static crate::pac::dac::Dac;
|
|
}
|
|
}
|
|
|
|
pub trait Instance: sealed::Instance + RccPeripheral + 'static {}
|
|
dma_trait!(DmaCh1, Instance);
|
|
dma_trait!(DmaCh2, Instance);
|
|
|
|
/// Marks a pin that can be used with the DAC
|
|
pub trait DacPin<T: Instance, const C: u8>: crate::gpio::Pin + 'static {}
|
|
|
|
foreach_peripheral!(
|
|
(dac, $inst:ident) => {
|
|
// H7 uses single bit for both DAC1 and DAC2, this is a hack until a proper fix is implemented
|
|
#[cfg(any(rcc_h7, rcc_h7rm0433))]
|
|
impl crate::rcc::sealed::RccPeripheral for peripherals::$inst {
|
|
fn frequency() -> crate::time::Hertz {
|
|
critical_section::with(|_| unsafe { crate::rcc::get_freqs().apb1 })
|
|
}
|
|
|
|
fn enable_and_reset() {
|
|
critical_section::with(|_| {
|
|
crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(true));
|
|
crate::pac::RCC.apb1lrstr().modify(|w| w.set_dac12rst(false));
|
|
crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(true));
|
|
})
|
|
}
|
|
|
|
fn disable() {
|
|
critical_section::with(|_| {
|
|
crate::pac::RCC.apb1lenr().modify(|w| w.set_dac12en(false))
|
|
})
|
|
}
|
|
}
|
|
|
|
#[cfg(any(rcc_h7, rcc_h7rm0433))]
|
|
impl crate::rcc::RccPeripheral for peripherals::$inst {}
|
|
|
|
impl crate::dac::sealed::Instance for peripherals::$inst {
|
|
fn regs() -> &'static crate::pac::dac::Dac {
|
|
&crate::pac::$inst
|
|
}
|
|
}
|
|
|
|
impl crate::dac::Instance for peripherals::$inst {}
|
|
};
|
|
);
|
|
|
|
macro_rules! impl_dac_pin {
|
|
($inst:ident, $pin:ident, $ch:expr) => {
|
|
impl crate::dac::DacPin<peripherals::$inst, $ch> for crate::peripherals::$pin {}
|
|
};
|
|
}
|