64964bd614
On STM32L4[7-A]xx, STM32L5xxx and STM32U5xxx chips, the GPIOG[2..15] pins are only available once the IOSV bit has been set in PWR->CR2 (U5 chips have the bit in a funkier register). This is meant to allow the user to have control over this power supply, so the GPIOG pins are initially insulated, until the user wishes to un-insulate them (or something like that?). For most applications, though, the VDDIO2 is connected to the VDD line, and this behavior only gets in the way and causes confusing issues. This submission adds an option in `embassy_stm32::Config`, called `enable_independent_io_supply`, which simply enables the IOSV bit. It is only available on chips for which I could find a mention of IOSV (STM32L4 and STM32L5) or IO2SV (STM32U5).
361 lines
11 KiB
Rust
361 lines
11 KiB
Rust
#![cfg_attr(not(test), no_std)]
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#![allow(async_fn_in_trait)]
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#![cfg_attr(
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docsrs,
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doc = "<div style='padding:30px;background:#810;color:#fff;text-align:center;'><p>You might want to <a href='https://docs.embassy.dev/embassy-stm32'>browse the `embassy-stm32` documentation on the Embassy website</a> instead.</p><p>The documentation here on `docs.rs` is built for a single chip only (STM32H755 in particular), while on the Embassy website you can pick your exact chip from the top menu. Available peripherals and their APIs change depending on the chip.</p></div>\n\n"
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)]
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#![doc = include_str!("../README.md")]
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#![warn(missing_docs)]
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//! ## Feature flags
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#![doc = document_features::document_features!(feature_label = r#"<span class="stab portability"><code>{feature}</code></span>"#)]
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// This must go FIRST so that all the other modules see its macros.
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mod fmt;
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include!(concat!(env!("OUT_DIR"), "/_macros.rs"));
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// Utilities
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pub mod time;
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mod traits;
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// Always-present hardware
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pub mod dma;
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pub mod gpio;
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pub mod rcc;
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#[cfg(feature = "_time-driver")]
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mod time_driver;
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pub mod timer;
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// Sometimes-present hardware
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#[cfg(adc)]
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pub mod adc;
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#[cfg(can)]
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pub mod can;
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#[cfg(crc)]
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pub mod crc;
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#[cfg(cryp)]
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pub mod cryp;
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#[cfg(dac)]
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pub mod dac;
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#[cfg(dcmi)]
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pub mod dcmi;
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#[cfg(eth)]
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pub mod eth;
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#[cfg(feature = "exti")]
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pub mod exti;
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pub mod flash;
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#[cfg(fmc)]
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pub mod fmc;
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#[cfg(hash)]
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pub mod hash;
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#[cfg(hrtim)]
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pub mod hrtim;
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#[cfg(i2c)]
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pub mod i2c;
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#[cfg(all(spi_v1, rcc_f4))]
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pub mod i2s;
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#[cfg(stm32wb)]
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pub mod ipcc;
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#[cfg(feature = "low-power")]
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pub mod low_power;
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#[cfg(opamp)]
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pub mod opamp;
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#[cfg(quadspi)]
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pub mod qspi;
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#[cfg(rng)]
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pub mod rng;
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#[cfg(all(rtc, not(rtc_v1)))]
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pub mod rtc;
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#[cfg(sai)]
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pub mod sai;
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#[cfg(sdmmc)]
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pub mod sdmmc;
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#[cfg(spi)]
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pub mod spi;
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#[cfg(ucpd)]
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pub mod ucpd;
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#[cfg(uid)]
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pub mod uid;
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#[cfg(usart)]
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pub mod usart;
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#[cfg(any(usb, otg))]
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pub mod usb;
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#[cfg(iwdg)]
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pub mod wdg;
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// This must go last, so that it sees all the impl_foo! macros defined earlier.
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pub(crate) mod _generated {
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#![allow(dead_code)]
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#![allow(unused_imports)]
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#![allow(non_snake_case)]
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#![allow(missing_docs)]
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include!(concat!(env!("OUT_DIR"), "/_generated.rs"));
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}
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pub use crate::_generated::interrupt;
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/// Macro to bind interrupts to handlers.
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///
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/// This defines the right interrupt handlers, and creates a unit struct (like `struct Irqs;`)
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/// and implements the right [`Binding`]s for it. You can pass this struct to drivers to
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/// prove at compile-time that the right interrupts have been bound.
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///
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/// Example of how to bind one interrupt:
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///
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/// ```rust,ignore
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/// use embassy_stm32::{bind_interrupts, usb, peripherals};
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///
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/// bind_interrupts!(struct Irqs {
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/// OTG_FS => usb::InterruptHandler<peripherals::USB_OTG_FS>;
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/// });
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/// ```
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///
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/// Example of how to bind multiple interrupts, and multiple handlers to each interrupt, in a single macro invocation:
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///
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/// ```rust,ignore
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/// use embassy_stm32::{bind_interrupts, i2c, peripherals};
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///
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/// bind_interrupts!(struct Irqs {
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/// I2C1 => i2c::EventInterruptHandler<peripherals::I2C1>, i2c::ErrorInterruptHandler<peripherals::I2C1>;
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/// I2C2_3 => i2c::EventInterruptHandler<peripherals::I2C2>, i2c::ErrorInterruptHandler<peripherals::I2C2>,
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/// i2c::EventInterruptHandler<peripherals::I2C3>, i2c::ErrorInterruptHandler<peripherals::I2C3>;
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/// });
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/// ```
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// developer note: this macro can't be in `embassy-hal-internal` due to the use of `$crate`.
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#[macro_export]
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macro_rules! bind_interrupts {
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($vis:vis struct $name:ident { $($irq:ident => $($handler:ty),*;)* }) => {
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#[derive(Copy, Clone)]
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$vis struct $name;
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$(
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#[allow(non_snake_case)]
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#[no_mangle]
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unsafe extern "C" fn $irq() {
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$(
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<$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt();
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)*
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}
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$(
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unsafe impl $crate::interrupt::typelevel::Binding<$crate::interrupt::typelevel::$irq, $handler> for $name {}
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)*
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)*
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};
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}
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// Reexports
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pub use _generated::{peripherals, Peripherals};
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pub use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
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#[cfg(feature = "unstable-pac")]
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pub use stm32_metapac as pac;
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#[cfg(not(feature = "unstable-pac"))]
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pub(crate) use stm32_metapac as pac;
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use crate::interrupt::Priority;
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#[cfg(feature = "rt")]
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pub use crate::pac::NVIC_PRIO_BITS;
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use crate::rcc::SealedRccPeripheral;
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/// `embassy-stm32` global configuration.
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#[non_exhaustive]
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pub struct Config {
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/// RCC config.
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pub rcc: rcc::Config,
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/// Enable debug during sleep and stop.
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///
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/// May incrase power consumption. Defaults to true.
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#[cfg(dbgmcu)]
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pub enable_debug_during_sleep: bool,
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/// On low-power boards (eg. `stm32l4`, `stm32l5` and `stm32u5`),
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/// some GPIO pins are powered by an auxiliary, independent power supply (`VDDIO2`),
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/// which needs to be enabled before these pins can be used.
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///
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/// May increase power consumption. Defaults to true.
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#[cfg(any(stm32l4, stm32l5, stm32u5))]
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pub enable_independent_io_supply: bool,
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/// BDMA interrupt priority.
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///
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/// Defaults to P0 (highest).
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#[cfg(bdma)]
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pub bdma_interrupt_priority: Priority,
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/// DMA interrupt priority.
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///
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/// Defaults to P0 (highest).
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#[cfg(dma)]
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pub dma_interrupt_priority: Priority,
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/// GPDMA interrupt priority.
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///
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/// Defaults to P0 (highest).
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#[cfg(gpdma)]
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pub gpdma_interrupt_priority: Priority,
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/// Enables UCPD1 dead battery functionality.
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///
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/// Defaults to false (disabled).
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#[cfg(peri_ucpd1)]
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pub enable_ucpd1_dead_battery: bool,
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/// Enables UCPD2 dead battery functionality.
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///
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/// Defaults to false (disabled).
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#[cfg(peri_ucpd2)]
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pub enable_ucpd2_dead_battery: bool,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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rcc: Default::default(),
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#[cfg(dbgmcu)]
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enable_debug_during_sleep: true,
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#[cfg(any(stm32l4, stm32l5, stm32u5))]
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enable_independent_io_supply: true,
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#[cfg(bdma)]
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bdma_interrupt_priority: Priority::P0,
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#[cfg(dma)]
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dma_interrupt_priority: Priority::P0,
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#[cfg(gpdma)]
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gpdma_interrupt_priority: Priority::P0,
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#[cfg(peri_ucpd1)]
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enable_ucpd1_dead_battery: false,
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#[cfg(peri_ucpd2)]
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enable_ucpd2_dead_battery: false,
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}
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}
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}
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/// Initialize the `embassy-stm32` HAL with the provided configuration.
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///
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/// This returns the peripheral singletons that can be used for creating drivers.
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///
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/// This should only be called once at startup, otherwise it panics.
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pub fn init(config: Config) -> Peripherals {
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critical_section::with(|cs| {
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let p = Peripherals::take_with_cs(cs);
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#[cfg(dbgmcu)]
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crate::pac::DBGMCU.cr().modify(|cr| {
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#[cfg(any(dbgmcu_h5))]
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{
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cr.set_stop(config.enable_debug_during_sleep);
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cr.set_standby(config.enable_debug_during_sleep);
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}
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#[cfg(any(dbgmcu_f0, dbgmcu_c0, dbgmcu_g0, dbgmcu_u5, dbgmcu_wba, dbgmcu_l5))]
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{
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cr.set_dbg_stop(config.enable_debug_during_sleep);
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cr.set_dbg_standby(config.enable_debug_during_sleep);
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}
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#[cfg(any(
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dbgmcu_f1, dbgmcu_f2, dbgmcu_f3, dbgmcu_f4, dbgmcu_f7, dbgmcu_g4, dbgmcu_f7, dbgmcu_l0, dbgmcu_l1,
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dbgmcu_l4, dbgmcu_wb, dbgmcu_wl
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))]
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{
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cr.set_dbg_sleep(config.enable_debug_during_sleep);
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cr.set_dbg_stop(config.enable_debug_during_sleep);
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cr.set_dbg_standby(config.enable_debug_during_sleep);
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}
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#[cfg(dbgmcu_h7)]
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{
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cr.set_d1dbgcken(config.enable_debug_during_sleep);
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cr.set_d3dbgcken(config.enable_debug_during_sleep);
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cr.set_dbgsleep_d1(config.enable_debug_during_sleep);
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cr.set_dbgstby_d1(config.enable_debug_during_sleep);
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cr.set_dbgstop_d1(config.enable_debug_during_sleep);
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}
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});
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#[cfg(not(any(stm32f1, stm32wb, stm32wl)))]
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peripherals::SYSCFG::enable_and_reset_with_cs(cs);
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#[cfg(not(any(stm32h5, stm32h7, stm32wb, stm32wl)))]
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peripherals::PWR::enable_and_reset_with_cs(cs);
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#[cfg(not(any(stm32f2, stm32f4, stm32f7, stm32l0, stm32h5, stm32h7)))]
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peripherals::FLASH::enable_and_reset_with_cs(cs);
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// Enable the VDDIO2 power supply on chips that have it.
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// Note that this requires the PWR peripheral to be enabled first.
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#[cfg(any(stm32l4, stm32l5))]
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{
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crate::pac::PWR.cr2().modify(|w| {
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// The official documentation states that we should ideally enable VDDIO2
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// through the PVME2 bit, but it looks like this bit
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w.set_iosv(config.enable_independent_io_supply);
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});
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}
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#[cfg(stm32u5)]
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{
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crate::pac::PWR.svmcr().modify(|w| {
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w.set_io2sv(config.enable_independent_io_supply);
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});
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}
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// dead battery functionality is still present on these
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// chips despite them not having UCPD- disable it
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#[cfg(any(stm32g070, stm32g0b0))]
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{
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crate::pac::SYSCFG.cfgr1().modify(|w| {
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w.set_ucpd1_strobe(true);
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w.set_ucpd2_strobe(true);
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});
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}
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unsafe {
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#[cfg(ucpd)]
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ucpd::init(
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cs,
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#[cfg(peri_ucpd1)]
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config.enable_ucpd1_dead_battery,
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#[cfg(peri_ucpd2)]
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config.enable_ucpd2_dead_battery,
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);
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#[cfg(feature = "_split-pins-enabled")]
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crate::pac::SYSCFG.pmcr().modify(|pmcr| {
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#[cfg(feature = "split-pa0")]
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pmcr.set_pa0so(true);
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#[cfg(feature = "split-pa1")]
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pmcr.set_pa1so(true);
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#[cfg(feature = "split-pc2")]
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pmcr.set_pc2so(true);
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#[cfg(feature = "split-pc3")]
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pmcr.set_pc3so(true);
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});
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gpio::init(cs);
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dma::init(
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cs,
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#[cfg(bdma)]
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config.bdma_interrupt_priority,
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#[cfg(dma)]
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config.dma_interrupt_priority,
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#[cfg(gpdma)]
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config.gpdma_interrupt_priority,
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);
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#[cfg(feature = "exti")]
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exti::init(cs);
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rcc::init(config.rcc);
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// must be after rcc init
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#[cfg(feature = "_time-driver")]
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time_driver::init(cs);
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#[cfg(feature = "low-power")]
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{
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crate::rcc::REFCOUNT_STOP2 = 0;
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crate::rcc::REFCOUNT_STOP1 = 0;
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}
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}
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p
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})
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}
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