5e271ff31b
`select(rx.receive(), tx.transmit()` had subtle interrupt enable race conditions. Combine receiver and transmitter into one new `PdPhy` struct to disallow the problematic pattern. Scanning through the USB PD 2.0 specification there is no need to have RX and TX running concurrently (after all the USB PD communication is half-duplex).
447 lines
14 KiB
Rust
447 lines
14 KiB
Rust
//! USB Type-C/USB Power Delivery Interface (UCPD)
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// Implementation Notes
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//
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// As of Feb. 2024 the UCPD peripheral is availalbe on: G0, G4, H5, L5, U5
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//
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// Cube HAL LL Driver (g0):
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// https://github.com/STMicroelectronics/stm32g0xx_hal_driver/blob/v1.4.6/Inc/stm32g0xx_ll_ucpd.h
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// https://github.com/STMicroelectronics/stm32g0xx_hal_driver/blob/v1.4.6/Src/stm32g0xx_ll_ucpd.c
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// Except for a the `LL_UCPD_RxAnalogFilterEnable/Disable()` functions the Cube HAL implementation of
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// all families is the same.
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//
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// Dead battery pull-down resistors functionality is enabled by default on startup and must
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// be disabled by setting a bit in PWR/SYSCFG registers. The exact name and location for that
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// bit is different for each familily.
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use core::future::poll_fn;
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use core::marker::PhantomData;
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use core::task::Poll;
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use embassy_hal_internal::drop::OnDrop;
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use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
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use embassy_sync::waitqueue::AtomicWaker;
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use crate::dma::{AnyChannel, Request, Transfer, TransferOptions};
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use crate::interrupt;
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use crate::pac::ucpd::vals::{Anamode, Ccenable, PscUsbpdclk, Txmode};
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pub use crate::pac::ucpd::vals::{Phyccsel as CcSel, TypecVstateCc as CcVState};
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use crate::rcc::RccPeripheral;
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/// Pull-up or Pull-down resistor state of both CC lines.
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#[derive(Debug, Clone, Copy, PartialEq)]
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pub enum CcPull {
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/// Analog PHY for CC pin disabled.
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Disabled,
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/// Rd=5.1k pull-down resistor enabled when the corresponding DBCC pin is high.
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SinkDeadBattery,
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/// Rd=5.1k pull-down resistor.
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Sink,
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/// Rp=56k pull-up resistor to indicate default USB power.
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SourceDefaultUsb,
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/// Rp=22k pull-up resistor to indicate support for up to 1.5A.
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Source1_5A,
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/// Rp=10k pull-up resistor to indicate support for up to 3.0A.
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Source3_0A,
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}
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/// UCPD driver.
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pub struct Ucpd<'d, T: Instance> {
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_peri: PeripheralRef<'d, T>,
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}
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impl<'d, T: Instance> Drop for Ucpd<'d, T> {
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fn drop(&mut self) {
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T::REGS.cfgr1().write(|w| w.set_ucpden(false));
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}
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}
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impl<'d, T: Instance> Ucpd<'d, T> {
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/// Creates a new UCPD driver instance.
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pub fn new(
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peri: impl Peripheral<P = T> + 'd,
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_cc1: impl Peripheral<P = impl Cc1Pin<T>> + 'd,
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_cc2: impl Peripheral<P = impl Cc2Pin<T>> + 'd,
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cc_pull: CcPull,
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) -> Self {
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T::enable_and_reset();
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let r = T::REGS;
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r.cfgr1().write(|w| {
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// "The receiver is designed to work in the clock frequency range from 6 to 18 MHz.
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// However, the optimum performance is ensured in the range from 6 to 12 MHz"
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// UCPD is driven by HSI16 (16MHz internal oscillator), which we need to divide by 2.
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w.set_psc_usbpdclk(PscUsbpdclk::DIV2);
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// Prescaler to produce a target half-bit frequency of 600kHz which is required
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// to produce transmit with a nominal nominal bit rate of 300Kbps+-10% using
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// biphase mark coding (BMC, aka differential manchester coding).
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// A divider of 13 gives the target frequency closest to spec (~615kHz, 1.625us)
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// but we go with the (hopefully well tested) default value used by the Cube HAL
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// which is 14 divides the clock down to ~571kHz, 1.75us.
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w.set_hbitclkdiv(14 - 1);
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// Time window for detecting non-idle (12-20us).
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// 1.75us * 8 = 14us.
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w.set_transwin(8 - 1);
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// Time from the end of last bit of a Frame until the start of the first bit of the
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// next Preamble (min 25us).
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// 1.75us * 17 = ~30us
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w.set_ifrgap(17 - 1);
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w.set_ucpden(true);
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});
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r.cr().write(|w| {
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w.set_anamode(if cc_pull == CcPull::Sink {
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Anamode::SINK
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} else {
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Anamode::SOURCE
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});
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w.set_anasubmode(match cc_pull {
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CcPull::SourceDefaultUsb => 1,
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CcPull::Source1_5A => 2,
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CcPull::Source3_0A => 3,
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_ => 0,
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});
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w.set_ccenable(if cc_pull != CcPull::SinkDeadBattery {
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Ccenable::BOTH
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} else {
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Ccenable::DISABLED
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});
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// Make sure detector is enabled on both pins.
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w.set_cc1tcdis(false);
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w.set_cc2tcdis(false);
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});
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// Disable dead-battery pull-down resistors which are enabled by default on boot.
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critical_section::with(|_| {
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// TODO: other families
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#[cfg(stm32g4)]
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crate::pac::PWR
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.cr3()
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.modify(|w| w.set_ucpd1_dbdis(cc_pull != CcPull::SinkDeadBattery));
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});
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into_ref!(peri);
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Self { _peri: peri }
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}
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/// Returns the current voltage level of CC1 and CC2 pin as tuple.
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///
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/// Interpretation of the voltage levels depends on the configured CC line
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/// pull-up/pull-down resistance.
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pub fn cc_vstate(&self) -> (CcVState, CcVState) {
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let sr = T::REGS.sr().read();
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(sr.typec_vstate_cc1(), sr.typec_vstate_cc2())
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}
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/// Waits for a change in voltage state on either CC line.
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pub async fn wait_for_cc_vstate_change(&self) -> (CcVState, CcVState) {
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let _on_drop = OnDrop::new(|| self.enable_cc_interrupts(false));
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let prev_vstate = self.cc_vstate();
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poll_fn(|cx| {
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let vstate = self.cc_vstate();
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if vstate != prev_vstate {
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Poll::Ready(vstate)
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} else {
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T::waker().register(cx.waker());
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self.enable_cc_interrupts(true);
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Poll::Pending
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}
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})
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.await
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}
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fn enable_cc_interrupts(&self, enable: bool) {
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T::REGS.imr().modify(|w| {
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w.set_typecevt1ie(enable);
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w.set_typecevt2ie(enable);
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});
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}
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/// Returns PD receiver and transmitter.
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pub fn pd_phy(
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&mut self,
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rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
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tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
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cc_sel: CcSel,
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) -> PdPhy<'_, T> {
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let r = T::REGS;
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// TODO: Currently only SOP messages are supported.
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r.tx_ordsetr().write(|w| w.set_txordset(0b10001_11000_11000_11000));
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r.cfgr1().modify(|w| {
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// TODO: Currently only SOP messages are supported.
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w.set_rxordseten(0x1);
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// Enable DMA
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w.set_txdmaen(true);
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w.set_rxdmaen(true);
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});
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// Enable the receiver on one of the two CC lines.
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r.cr().modify(|w| {
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w.set_phyccsel(cc_sel);
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w.set_phyrxen(true);
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});
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into_ref!(rx_dma, tx_dma);
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let rx_dma_req = rx_dma.request();
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let tx_dma_req = tx_dma.request();
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PdPhy {
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_ucpd: self,
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rx_dma_ch: rx_dma.map_into(),
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rx_dma_req,
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tx_dma_ch: tx_dma.map_into(),
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tx_dma_req,
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}
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}
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}
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/// Receive Error.
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#[derive(Debug, Clone, Copy)]
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pub enum RxError {
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/// Incorrect CRC or truncated message (a line becoming static before EOP is met).
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Crc,
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/// Provided buffer was too small for the received message.
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Overrun,
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}
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/// Transmit Error.
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#[derive(Debug, Clone, Copy)]
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pub enum TxError {
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/// Concurrent receive in progress or excessive noise on the line.
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Discarded,
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}
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/// Power Delivery (PD) PHY.
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pub struct PdPhy<'d, T: Instance> {
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_ucpd: &'d Ucpd<'d, T>,
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rx_dma_ch: PeripheralRef<'d, AnyChannel>,
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rx_dma_req: Request,
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tx_dma_ch: PeripheralRef<'d, AnyChannel>,
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tx_dma_req: Request,
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}
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impl<'d, T: Instance> Drop for PdPhy<'d, T> {
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fn drop(&mut self) {
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T::REGS.cr().modify(|w| w.set_phyrxen(false));
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}
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}
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impl<'d, T: Instance> PdPhy<'d, T> {
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/// Receives a PD message into the provided buffer.
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///
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/// Returns the number of received bytes or an error.
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pub async fn receive(&mut self, buf: &mut [u8]) -> Result<usize, RxError> {
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let r = T::REGS;
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// Check if a message is already being received. If yes, wait until its
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// done, ignore errors and try to receive the next message.
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if r.sr().read().rxorddet() {
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let _ = self.wait_rx_done().await;
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r.rxdr().read(); // Clear the RX buffer.
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}
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// Keep the DMA transfer alive so its drop code does not stop it right away.
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let dma = unsafe {
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// Disable the DMA complete interrupt because the end of packet is
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// signaled by the UCPD receiver. When the DMA buffer is too short
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// DMA stops by itself and the overrun RXOVR flag of UCPD is set.
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let mut transfer_options = TransferOptions::default();
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transfer_options.complete_transfer_ir = false;
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Transfer::new_read(
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&self.rx_dma_ch,
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self.rx_dma_req,
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r.rxdr().as_ptr() as *mut u8,
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buf,
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transfer_options,
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)
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};
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self.wait_rx_done().await?;
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// Make sure the the last byte to byte was fetched by DMA.
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while r.sr().read().rxne() {
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if dma.get_remaining_transfers() == 0 {
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return Err(RxError::Overrun);
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}
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}
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Ok(r.rx_payszr().read().rxpaysz().into())
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}
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async fn wait_rx_done(&self) -> Result<(), RxError> {
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let _on_drop = OnDrop::new(|| self.enable_rx_interrupt(false));
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poll_fn(|cx| {
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let r = T::REGS;
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let sr = r.sr().read();
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if sr.rxmsgend() {
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let ret = if sr.rxovr() {
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Err(RxError::Overrun)
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} else if sr.rxerr() {
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Err(RxError::Crc)
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} else {
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Ok(())
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};
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// Message received, clear interrupt flags.
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r.icr().write(|w| {
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w.set_rxorddetcf(true);
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w.set_rxovrcf(true);
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w.set_rxmsgendcf(true);
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});
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Poll::Ready(ret)
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} else {
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T::waker().register(cx.waker());
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self.enable_rx_interrupt(true);
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Poll::Pending
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}
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})
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.await
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}
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fn enable_rx_interrupt(&self, enable: bool) {
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T::REGS.imr().modify(|w| w.set_rxmsgendie(enable));
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}
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/// Transmits a PD message.
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pub async fn transmit(&mut self, buf: &[u8]) -> Result<(), TxError> {
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let r = T::REGS;
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// When a previous transmission was dropped before it had finished it
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// might still be running because there is no way to abort an ongoing
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// message transmission. Wait for it to finish but ignore errors.
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if r.cr().read().txsend() {
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let _ = self.wait_tx_done().await;
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}
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// Clear the TX interrupt flags.
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T::REGS.icr().write(|w| {
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w.set_txmsgdisccf(true);
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w.set_txmsgsentcf(true);
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});
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// Start the DMA and let it do its thing in the background.
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let _dma = unsafe {
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Transfer::new_write(
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&self.tx_dma_ch,
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self.tx_dma_req,
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buf,
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r.txdr().as_ptr() as *mut u8,
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TransferOptions::default(),
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)
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};
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// Configure and start the transmission.
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r.tx_payszr().write(|w| w.set_txpaysz(buf.len() as _));
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r.cr().modify(|w| {
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w.set_txmode(Txmode::PACKET);
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w.set_txsend(true);
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});
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self.wait_tx_done().await
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}
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async fn wait_tx_done(&self) -> Result<(), TxError> {
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let _on_drop = OnDrop::new(|| self.enable_tx_interrupts(false));
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poll_fn(|cx| {
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let r = T::REGS;
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if r.sr().read().txmsgdisc() {
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Poll::Ready(Err(TxError::Discarded))
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} else if r.sr().read().txmsgsent() {
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Poll::Ready(Ok(()))
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} else {
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T::waker().register(cx.waker());
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self.enable_tx_interrupts(true);
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Poll::Pending
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}
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})
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.await
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}
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fn enable_tx_interrupts(&self, enable: bool) {
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T::REGS.imr().modify(|w| {
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w.set_txmsgdiscie(enable);
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w.set_txmsgsentie(enable);
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});
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}
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}
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/// Interrupt handler.
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pub struct InterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
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unsafe fn on_interrupt() {
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let r = T::REGS;
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let sr = r.sr().read();
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if sr.typecevt1() || sr.typecevt2() {
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r.icr().write(|w| {
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w.set_typecevt1cf(true);
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w.set_typecevt2cf(true);
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});
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}
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if sr.rxmsgend() {
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r.imr().modify(|w| w.set_rxmsgendie(false));
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}
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if sr.txmsgdisc() || sr.txmsgsent() {
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r.imr().modify(|w| {
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w.set_txmsgdiscie(false);
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w.set_txmsgsentie(false);
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});
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}
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// Wake the task to clear and re-enabled interrupts.
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T::waker().wake();
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}
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}
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/// UCPD instance trait.
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pub trait Instance: sealed::Instance + RccPeripheral {}
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pub(crate) mod sealed {
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pub trait Instance {
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type Interrupt: crate::interrupt::typelevel::Interrupt;
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const REGS: crate::pac::ucpd::Ucpd;
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fn waker() -> &'static embassy_sync::waitqueue::AtomicWaker;
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}
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}
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foreach_interrupt!(
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($inst:ident, ucpd, UCPD, GLOBAL, $irq:ident) => {
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impl sealed::Instance for crate::peripherals::$inst {
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type Interrupt = crate::interrupt::typelevel::$irq;
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const REGS: crate::pac::ucpd::Ucpd = crate::pac::$inst;
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fn waker() -> &'static AtomicWaker {
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static WAKER: AtomicWaker = AtomicWaker::new();
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&WAKER
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}
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}
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impl Instance for crate::peripherals::$inst {}
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};
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);
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pin_trait!(Cc1Pin, Instance);
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pin_trait!(Cc2Pin, Instance);
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dma_trait!(TxDma, Instance);
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dma_trait!(RxDma, Instance);
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