187 lines
6.6 KiB
Rust
187 lines
6.6 KiB
Rust
//! Daisy Seed rev.7(with PCM3060 codec)
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//! https://electro-smith.com/products/daisy-seed
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#![no_std]
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#![no_main]
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use embassy_executor::Spawner;
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use grounded::uninit::GroundedArrayCell;
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use hal::rcc::*;
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use hal::sai::*;
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use hal::time::Hertz;
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use {defmt_rtt as _, embassy_stm32 as hal, panic_probe as _};
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const BLOCK_LENGTH: usize = 32; // 32 samples
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const HALF_DMA_BUFFER_LENGTH: usize = BLOCK_LENGTH * 2; // 2 channels
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const DMA_BUFFER_LENGTH: usize = HALF_DMA_BUFFER_LENGTH * 2; // 2 half-blocks
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const SAMPLE_RATE: u32 = 48000;
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//DMA buffer must be in special region. Refer https://embassy.dev/book/#_stm32_bdma_only_working_out_of_some_ram_regions
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#[link_section = ".sram1_bss"]
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static mut TX_BUFFER: GroundedArrayCell<u32, DMA_BUFFER_LENGTH> = GroundedArrayCell::uninit();
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#[link_section = ".sram1_bss"]
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static mut RX_BUFFER: GroundedArrayCell<u32, DMA_BUFFER_LENGTH> = GroundedArrayCell::uninit();
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#[embassy_executor::main]
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async fn main(_spawner: Spawner) {
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let mut config = hal::Config::default();
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config.rcc.pll1 = Some(Pll {
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source: PllSource::HSE,
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prediv: PllPreDiv::DIV4,
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mul: PllMul::MUL200,
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divp: Some(PllDiv::DIV2),
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divq: Some(PllDiv::DIV5),
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divr: Some(PllDiv::DIV2),
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});
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config.rcc.pll3 = Some(Pll {
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source: PllSource::HSE,
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prediv: PllPreDiv::DIV6,
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mul: PllMul::MUL295,
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divp: Some(PllDiv::DIV16),
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divq: Some(PllDiv::DIV4),
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divr: Some(PllDiv::DIV32),
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});
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config.rcc.sys = Sysclk::PLL1_P;
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config.rcc.mux.sai1sel = hal::pac::rcc::vals::Saisel::PLL3_P;
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config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
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config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
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config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
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config.rcc.apb3_pre = APBPrescaler::DIV2; // 100 Mhz
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config.rcc.apb4_pre = APBPrescaler::DIV2; // 100 Mhz
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config.rcc.hse = Some(Hse {
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freq: Hertz::mhz(16),
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mode: HseMode::Oscillator,
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});
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let p = hal::init(config);
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let (sub_block_tx, sub_block_rx) = hal::sai::split_subblocks(p.SAI1);
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let kernel_clock = hal::rcc::frequency::<hal::peripherals::SAI1>().0;
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let mclk_div = mclk_div_from_u8((kernel_clock / (SAMPLE_RATE * 256)) as u8);
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let mut tx_config = hal::sai::Config::default();
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tx_config.mode = Mode::Master;
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tx_config.tx_rx = TxRx::Transmitter;
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tx_config.sync_output = true;
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tx_config.clock_strobe = ClockStrobe::Falling;
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tx_config.master_clock_divider = mclk_div;
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tx_config.stereo_mono = StereoMono::Stereo;
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tx_config.data_size = DataSize::Data24;
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tx_config.bit_order = BitOrder::MsbFirst;
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tx_config.frame_sync_polarity = FrameSyncPolarity::ActiveHigh;
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tx_config.frame_sync_offset = FrameSyncOffset::OnFirstBit;
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tx_config.frame_length = 64;
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tx_config.frame_sync_active_level_length = embassy_stm32::sai::word::U7(32);
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tx_config.fifo_threshold = FifoThreshold::Quarter;
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let mut rx_config = tx_config.clone();
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rx_config.mode = Mode::Slave;
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rx_config.tx_rx = TxRx::Receiver;
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rx_config.sync_input = SyncInput::Internal;
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rx_config.clock_strobe = ClockStrobe::Rising;
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rx_config.sync_output = false;
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let tx_buffer: &mut [u32] = unsafe {
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TX_BUFFER.initialize_all_copied(0);
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let (ptr, len) = TX_BUFFER.get_ptr_len();
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core::slice::from_raw_parts_mut(ptr, len)
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};
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let mut sai_transmitter = Sai::new_asynchronous_with_mclk(
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sub_block_tx,
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p.PE5,
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p.PE6,
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p.PE4,
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p.PE2,
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p.DMA1_CH0,
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tx_buffer,
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tx_config,
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);
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let rx_buffer: &mut [u32] = unsafe {
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RX_BUFFER.initialize_all_copied(0);
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let (ptr, len) = RX_BUFFER.get_ptr_len();
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core::slice::from_raw_parts_mut(ptr, len)
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};
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let mut sai_receiver = Sai::new_synchronous(sub_block_rx, p.PE3, p.DMA1_CH1, rx_buffer, rx_config);
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sai_receiver.start();
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sai_transmitter.start();
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let mut buf = [0u32; HALF_DMA_BUFFER_LENGTH];
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loop {
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sai_receiver.read(&mut buf).await.unwrap();
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sai_transmitter.write(&buf).await.unwrap();
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}
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}
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const fn mclk_div_from_u8(v: u8) -> MasterClockDivider {
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match v {
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1 => MasterClockDivider::Div1,
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2 => MasterClockDivider::Div2,
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3 => MasterClockDivider::Div3,
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4 => MasterClockDivider::Div4,
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5 => MasterClockDivider::Div5,
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6 => MasterClockDivider::Div6,
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7 => MasterClockDivider::Div7,
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8 => MasterClockDivider::Div8,
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9 => MasterClockDivider::Div9,
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10 => MasterClockDivider::Div10,
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11 => MasterClockDivider::Div11,
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12 => MasterClockDivider::Div12,
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13 => MasterClockDivider::Div13,
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14 => MasterClockDivider::Div14,
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15 => MasterClockDivider::Div15,
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16 => MasterClockDivider::Div16,
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17 => MasterClockDivider::Div17,
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18 => MasterClockDivider::Div18,
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19 => MasterClockDivider::Div19,
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20 => MasterClockDivider::Div20,
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21 => MasterClockDivider::Div21,
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22 => MasterClockDivider::Div22,
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23 => MasterClockDivider::Div23,
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24 => MasterClockDivider::Div24,
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25 => MasterClockDivider::Div25,
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26 => MasterClockDivider::Div26,
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27 => MasterClockDivider::Div27,
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28 => MasterClockDivider::Div28,
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29 => MasterClockDivider::Div29,
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30 => MasterClockDivider::Div30,
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31 => MasterClockDivider::Div31,
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32 => MasterClockDivider::Div32,
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33 => MasterClockDivider::Div33,
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34 => MasterClockDivider::Div34,
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35 => MasterClockDivider::Div35,
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36 => MasterClockDivider::Div36,
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37 => MasterClockDivider::Div37,
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38 => MasterClockDivider::Div38,
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39 => MasterClockDivider::Div39,
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40 => MasterClockDivider::Div40,
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41 => MasterClockDivider::Div41,
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42 => MasterClockDivider::Div42,
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43 => MasterClockDivider::Div43,
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44 => MasterClockDivider::Div44,
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45 => MasterClockDivider::Div45,
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46 => MasterClockDivider::Div46,
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47 => MasterClockDivider::Div47,
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48 => MasterClockDivider::Div48,
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49 => MasterClockDivider::Div49,
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50 => MasterClockDivider::Div50,
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51 => MasterClockDivider::Div51,
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52 => MasterClockDivider::Div52,
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53 => MasterClockDivider::Div53,
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54 => MasterClockDivider::Div54,
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55 => MasterClockDivider::Div55,
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56 => MasterClockDivider::Div56,
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57 => MasterClockDivider::Div57,
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58 => MasterClockDivider::Div58,
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59 => MasterClockDivider::Div59,
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60 => MasterClockDivider::Div60,
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61 => MasterClockDivider::Div61,
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62 => MasterClockDivider::Div62,
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63 => MasterClockDivider::Div63,
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_ => panic!(),
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}
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}
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