658 lines
21 KiB
Rust
658 lines
21 KiB
Rust
//! TSC Peripheral Interface
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#![macro_use]
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/// Enums defined for peripheral parameters
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pub mod enums;
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use embassy_hal_internal::{into_ref, PeripheralRef};
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pub use enums::*;
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use crate::gpio::{AFType, AnyPin, Pull};
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use crate::pac::tsc::Tsc as Regs;
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use crate::rcc::RccPeripheral;
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use crate::{peripherals, Peripheral};
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const TSC_NUM_GROUPS: u32 = 8;
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/// Error type defined for TSC
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Error {
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/// Test error for TSC
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Test,
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}
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/// Pin type definition to control IO parameters
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pub enum PinType {
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/// Sensing channel pin connected to an electrode
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Channel,
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/// Sampling capacitor pin, one required for every pin group
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Sample,
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/// Shield pin connected to capacitive sensing shield
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Shield,
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}
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/// Unclear
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pub struct TscGroup {}
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/// Peripheral state
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#[derive(PartialEq, Clone, Copy)]
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pub enum State {
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/// Peripheral is being setup or reconfigured
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Reset,
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/// Ready to start acquisition
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Ready,
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/// In process of sensor acquisition
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Busy,
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/// Error occured during acquisition
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Error,
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}
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/// Individual group status checked after acquisition reported as complete
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/// For groups with multiple channel pins, may take longer because acquisitions
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/// are done sequentially. Check this status before pulling count for each
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/// sampled channel
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pub enum GroupStatus {
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/// Acquisition for channel still in progress
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Ongoing,
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/// Acquisition either not started or complete
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Complete,
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}
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/// Group identifier used to interrogate status
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#[allow(missing_docs)]
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pub enum Group {
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One,
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Two,
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Three,
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Four,
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Five,
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Six,
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#[cfg(any(tsc_v2, tsc_v3))]
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Seven,
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#[cfg(tsc_v3)]
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Eight,
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}
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impl Into<usize> for Group {
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fn into(self) -> usize {
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match self {
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Group::One => 0,
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Group::Two => 1,
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Group::Three => 2,
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Group::Four => 3,
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Group::Five => 4,
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Group::Six => 5,
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#[cfg(any(tsc_v2, tsc_v3))]
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Group::Seven => 6,
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#[cfg(tsc_v3)]
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Group::Eight => 7,
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}
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}
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}
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/// Peripheral configuration
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#[derive(Clone, Copy)]
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pub struct Config {
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/// Duration of high state of the charge transfer pulse
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pub ct_pulse_high_length: ChargeTransferPulseCycle,
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/// Duration of the low state of the charge transfer pulse
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pub ct_pulse_low_length: ChargeTransferPulseCycle,
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/// Enable/disable of spread spectrum feature
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pub spread_spectrum: bool,
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/// Adds variable number of periods of the SS clk to pulse high state
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pub spread_spectrum_deviation: SSDeviation,
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/// Selects AHB clock divider used to generate SS clk
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pub spread_spectrum_prescaler: bool,
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/// Selects AHB clock divider used to generate pulse generator clk
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pub pulse_generator_prescaler: PGPrescalerDivider,
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/// Maximum number of charge tranfer pulses that can be generated before error
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pub max_count_value: MaxCount,
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/// Defines config of all IOs when no ongoing acquisition
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pub io_default_mode: bool,
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/// Polarity of sync input pin
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pub synchro_pin_polarity: bool,
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/// Acquisition starts when start bit is set or with sync pin input
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pub acquisition_mode: bool,
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/// Enable max count interrupt
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pub max_count_interrupt: bool,
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/// Channel IO mask
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pub channel_ios: u32,
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/// Shield IO mask
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pub shield_ios: u32,
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/// Sampling IO mask
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pub sampling_ios: u32,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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ct_pulse_high_length: ChargeTransferPulseCycle::_1,
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ct_pulse_low_length: ChargeTransferPulseCycle::_1,
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spread_spectrum: false,
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spread_spectrum_deviation: SSDeviation::new(0).unwrap(),
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spread_spectrum_prescaler: false,
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pulse_generator_prescaler: PGPrescalerDivider::_1,
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max_count_value: MaxCount::_255,
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io_default_mode: false,
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synchro_pin_polarity: false,
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acquisition_mode: false,
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max_count_interrupt: false,
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channel_ios: 0,
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shield_ios: 0,
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sampling_ios: 0,
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}
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}
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}
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/// Pin struct that maintains usage
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#[allow(missing_docs)]
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#[allow(dead_code)]
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pub struct TscPin<'d, T> {
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pin: PeripheralRef<'d, T>,
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role: PinType,
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}
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/// Input structure for constructor containing peripherals
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#[allow(missing_docs)]
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pub struct PeriPin<T> {
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pub pin: T,
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pub role: PinType,
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}
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/// Pin group definition
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/// Pins are organized into groups of four IOs, all groups with a
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/// sampling channel must also have a sampling capacitor channel.
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#[allow(missing_docs)]
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pub struct PinGroup<'d, A> {
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pub d1: Option<TscPin<'d, A>>,
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pub d2: Option<TscPin<'d, A>>,
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pub d3: Option<TscPin<'d, A>>,
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pub d4: Option<TscPin<'d, A>>,
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}
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/// TSC driver
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pub struct Tsc<'d, T: Instance> {
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_peri: PeripheralRef<'d, T>,
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_g1: Option<PinGroup<'d, AnyPin>>,
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_g2: Option<PinGroup<'d, AnyPin>>,
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_g3: Option<PinGroup<'d, AnyPin>>,
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_g4: Option<PinGroup<'d, AnyPin>>,
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_g5: Option<PinGroup<'d, AnyPin>>,
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_g6: Option<PinGroup<'d, AnyPin>>,
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#[cfg(any(tsc_v2, tsc_v3))]
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_g7: Option<PinGroup<'d, AnyPin>>,
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#[cfg(tsc_v3)]
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_g8: Option<PinGroup<'d, AnyPin>>,
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state: State,
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config: Config,
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}
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impl<'d, T: Instance> Tsc<'d, T> {
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/// Create new TSC driver
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pub fn new(
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peri: impl Peripheral<P = T> + 'd,
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// g1_d1: Option<PeriPin<impl Peripheral<P = impl G1IO1Pin<T>> + 'd>>,
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g1_d2: Option<PeriPin<impl Peripheral<P = impl G1IO2Pin<T>> + 'd>>,
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g1_d3: Option<PeriPin<impl Peripheral<P = impl G1IO3Pin<T>> + 'd>>,
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// g1_d4: Option<PeriPin<impl Peripheral<P = impl G1IO4Pin<T>> + 'd>>,
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// g2_d1: Option<impl Peripheral<P = impl G2IO1Pin<T>> + 'd>,
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// g2_d2: Option<impl Peripheral<P = impl G2IO2Pin<T>> + 'd>,
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g2_d3: Option<PeriPin<impl Peripheral<P = impl G2IO3Pin<T>> + 'd>>,
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g2_d4: Option<PeriPin<impl Peripheral<P = impl G2IO4Pin<T>> + 'd>>,
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// g3_d1: Option<impl Peripheral<P = impl G3IO1Pin<T>> + 'd>,
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// g3_d2: Option<impl Peripheral<P = impl G3IO2Pin<T>> + 'd>,
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// g3_d3: Option<impl Peripheral<P = impl G3IO3Pin<T>> + 'd>,
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// g3_d4: Option<impl Peripheral<P = impl G3IO4Pin<T>> + 'd>,
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g4_d1: Option<PeriPin<impl Peripheral<P = impl G4IO1Pin<T>> + 'd>>,
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g4_d2: Option<PeriPin<impl Peripheral<P = impl G4IO2Pin<T>> + 'd>>,
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// g4_d3: Option<impl Peripheral<P = impl G4IO3Pin<T>> + 'd>,
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// g4_d4: Option<impl Peripheral<P = impl G4IO4Pin<T>> + 'd>,
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// g5_d1: Option<impl Peripheral<P = impl G5IO1Pin<T>> + 'd>,
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// g5_d2: Option<impl Peripheral<P = impl G5IO2Pin<T>> + 'd>,
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// g5_d3: Option<impl Peripheral<P = impl G5IO3Pin<T>> + 'd>,
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// g5_d4: Option<impl Peripheral<P = impl G5IO4Pin<T>> + 'd>,
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// g6_d1: Option<impl Peripheral<P = impl G6IO1Pin<T>> + 'd>,
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// g6_d2: Option<impl Peripheral<P = impl G6IO2Pin<T>> + 'd>,
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// g6_d3: Option<impl Peripheral<P = impl G6IO3Pin<T>> + 'd>,
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// g6_d4: Option<impl Peripheral<P = impl G6IO4Pin<T>> + 'd>,
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// g7_d1: Option<impl Peripheral<P = impl G7IO1Pin<T>> + 'd>,
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// g7_d2: Option<impl Peripheral<P = impl G7IO2Pin<T>> + 'd>,
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// g7_d3: Option<impl Peripheral<P = impl G7IO3Pin<T>> + 'd>,
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// g7_d4: Option<impl Peripheral<P = impl G7IO4Pin<T>> + 'd>,
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// g8_d1: Option<impl Peripheral<P = impl G8IO1Pin<T>> + 'd>,
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// g8_d2: Option<impl Peripheral<P = impl G8IO2Pin<T>> + 'd>,
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// g8_d3: Option<impl Peripheral<P = impl G8IO3Pin<T>> + 'd>,
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// g8_d4: Option<impl Peripheral<P = impl G8IO4Pin<T>> + 'd>,
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config: Config,
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) -> Self {
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let g1_d2 = g1_d2.unwrap();
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let g1_d2_pin = g1_d2.pin;
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let g1_d3 = g1_d3.unwrap();
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let g1_d3_pin = g1_d3.pin;
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let g2_d3 = g2_d3.unwrap();
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let g2_d3_pin = g2_d3.pin;
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let g2_d4 = g2_d4.unwrap();
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let g2_d4_pin = g2_d4.pin;
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let g4_d1 = g4_d1.unwrap();
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let g4_d1_pin = g4_d1.pin;
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let g4_d2 = g4_d2.unwrap();
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let g4_d2_pin = g4_d2.pin;
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into_ref!(peri, g1_d2_pin, g1_d3_pin, g2_d3_pin, g2_d4_pin, g4_d1_pin, g4_d2_pin);
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// Configure pins
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match g1_d2.role {
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PinType::Channel => g1_d2_pin.set_as_af_pull(g1_d2_pin.af_num(), AFType::OutputPushPull, Pull::None),
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PinType::Sample => g1_d2_pin.set_as_af_pull(g1_d2_pin.af_num(), AFType::OutputOpenDrain, Pull::None),
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PinType::Shield => g1_d2_pin.set_as_af_pull(g1_d2_pin.af_num(), AFType::OutputPushPull, Pull::None),
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}
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match g1_d3.role {
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PinType::Channel => g1_d3_pin.set_as_af_pull(g1_d3_pin.af_num(), AFType::OutputPushPull, Pull::None),
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PinType::Sample => g1_d3_pin.set_as_af_pull(g1_d3_pin.af_num(), AFType::OutputOpenDrain, Pull::None),
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PinType::Shield => g1_d3_pin.set_as_af_pull(g1_d3_pin.af_num(), AFType::OutputPushPull, Pull::None),
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}
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let g1 = PinGroup {
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d1: None,
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d2: Some(TscPin {
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pin: g1_d2_pin.map_into(),
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role: g1_d2.role,
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}),
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d3: Some(TscPin {
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pin: g1_d3_pin.map_into(),
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role: g1_d3.role,
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}),
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d4: None,
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};
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match g2_d3.role {
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PinType::Channel => g2_d3_pin.set_as_af_pull(g2_d3_pin.af_num(), AFType::OutputPushPull, Pull::None),
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PinType::Sample => g2_d3_pin.set_as_af_pull(g2_d3_pin.af_num(), AFType::OutputOpenDrain, Pull::None),
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PinType::Shield => g2_d3_pin.set_as_af_pull(g2_d3_pin.af_num(), AFType::OutputPushPull, Pull::None),
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}
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match g2_d4.role {
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PinType::Channel => g2_d4_pin.set_as_af_pull(g2_d4_pin.af_num(), AFType::OutputPushPull, Pull::None),
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PinType::Sample => g2_d4_pin.set_as_af_pull(g2_d4_pin.af_num(), AFType::OutputOpenDrain, Pull::None),
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PinType::Shield => g2_d4_pin.set_as_af_pull(g2_d4_pin.af_num(), AFType::OutputPushPull, Pull::None),
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}
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let g2 = PinGroup {
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d1: None,
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d2: None,
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d3: Some(TscPin {
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pin: g2_d3_pin.map_into(),
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role: g2_d3.role,
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}),
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d4: Some(TscPin {
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pin: g2_d4_pin.map_into(),
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role: g2_d4.role,
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}),
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};
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match g4_d1.role {
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PinType::Channel => g4_d1_pin.set_as_af_pull(g4_d1_pin.af_num(), AFType::OutputPushPull, Pull::None),
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PinType::Sample => g4_d1_pin.set_as_af_pull(g4_d1_pin.af_num(), AFType::OutputOpenDrain, Pull::None),
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PinType::Shield => g4_d1_pin.set_as_af_pull(g4_d1_pin.af_num(), AFType::OutputPushPull, Pull::None),
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}
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match g4_d2.role {
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PinType::Channel => g4_d2_pin.set_as_af_pull(g4_d2_pin.af_num(), AFType::OutputPushPull, Pull::None),
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PinType::Sample => g4_d2_pin.set_as_af_pull(g4_d2_pin.af_num(), AFType::OutputOpenDrain, Pull::None),
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PinType::Shield => g4_d2_pin.set_as_af_pull(g4_d2_pin.af_num(), AFType::OutputPushPull, Pull::None),
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}
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let g4 = PinGroup {
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d1: Some(TscPin {
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pin: g4_d1_pin.map_into(),
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role: g4_d1.role,
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}),
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d2: Some(TscPin {
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pin: g4_d2_pin.map_into(),
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role: g4_d2.role,
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}),
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d3: None,
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d4: None,
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};
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// Need to check valid pin configuration input
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Self::new_inner(
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peri,
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Some(g1),
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Some(g2),
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None,
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Some(g4),
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None,
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None,
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#[cfg(any(tsc_v2, tsc_v3))]
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None,
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#[cfg(tsc_v3)]
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None,
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config,
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)
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}
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// fn configure_pin<'b, G: Pin>(pin: PeripheralRef<'b, G>, role: PinType) {
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// match role {
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// PinType::Channel => pin.set_as_af_pull(pin.af_num(), AFType::OutputPushPull, Pull::None),
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// PinType::Sample => {}
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// PinType::Shield => {}
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// }
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// }
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// fn filter_group() -> Option<PinGroup<'d>> {}
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fn extract_groups(io_mask: u32) -> u32 {
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let mut groups: u32 = 0;
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for idx in 0..TSC_NUM_GROUPS {
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if io_mask & (0x0F << idx * 4) != 0 {
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groups |= 1 << idx
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}
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}
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groups
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}
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fn new_inner(
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peri: impl Peripheral<P = T> + 'd,
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g1: Option<PinGroup<'d, AnyPin>>,
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g2: Option<PinGroup<'d, AnyPin>>,
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g3: Option<PinGroup<'d, AnyPin>>,
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g4: Option<PinGroup<'d, AnyPin>>,
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g5: Option<PinGroup<'d, AnyPin>>,
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g6: Option<PinGroup<'d, AnyPin>>,
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#[cfg(any(tsc_v2, tsc_v3))] g7: Option<PinGroup<'d, AnyPin>>,
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#[cfg(tsc_v3)] g8: Option<PinGroup<'d, AnyPin>>,
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config: Config,
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) -> Self {
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into_ref!(peri);
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T::enable_and_reset();
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T::REGS.cr().modify(|w| {
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w.set_tsce(true);
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w.set_ctph(config.ct_pulse_high_length.into());
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w.set_ctpl(config.ct_pulse_low_length.into());
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w.set_sse(config.spread_spectrum);
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// Prevent invalid configuration for pulse generator prescaler
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if config.ct_pulse_low_length == ChargeTransferPulseCycle::_1
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&& (config.pulse_generator_prescaler == PGPrescalerDivider::_1
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|| config.pulse_generator_prescaler == PGPrescalerDivider::_2)
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{
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w.set_pgpsc(PGPrescalerDivider::_4.into());
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} else if config.ct_pulse_low_length == ChargeTransferPulseCycle::_2
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&& config.pulse_generator_prescaler == PGPrescalerDivider::_1
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{
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w.set_pgpsc(PGPrescalerDivider::_2.into());
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} else {
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w.set_pgpsc(config.pulse_generator_prescaler.into());
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}
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w.set_ssd(config.spread_spectrum_deviation.into());
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w.set_sspsc(config.spread_spectrum_prescaler);
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w.set_mcv(config.max_count_value.into());
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w.set_syncpol(config.synchro_pin_polarity);
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w.set_am(config.acquisition_mode);
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});
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// Set IO configuration
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// Disable Schmitt trigger hysteresis on all used TSC IOs
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T::REGS
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.iohcr()
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.write(|w| w.0 = config.channel_ios | config.shield_ios | config.sampling_ios);
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// Set channel and shield IOs
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T::REGS.ioccr().write(|w| w.0 = config.channel_ios | config.shield_ios);
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// Set sampling IOs
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T::REGS.ioscr().write(|w| w.0 = config.sampling_ios);
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// Set the groups to be acquired
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T::REGS
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.iogcsr()
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.write(|w| w.0 = Self::extract_groups(config.channel_ios));
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// Disable interrupts
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T::REGS.ier().modify(|w| {
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w.set_eoaie(false);
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w.set_mceie(false);
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});
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// Clear flags
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T::REGS.icr().modify(|w| {
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w.set_eoaic(true);
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w.set_mceic(true);
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});
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Self {
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_peri: peri,
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_g1: g1,
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_g2: g2,
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_g3: g3,
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_g4: g4,
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_g5: g5,
|
|
_g6: g6,
|
|
#[cfg(any(tsc_v2, tsc_v3))]
|
|
_g7: g7,
|
|
#[cfg(tsc_v3)]
|
|
_g8: g8,
|
|
state: State::Ready,
|
|
config,
|
|
}
|
|
}
|
|
|
|
/// Start charge transfer acquisition
|
|
pub fn start(&mut self) {
|
|
self.state = State::Busy;
|
|
|
|
// Disable interrupts
|
|
T::REGS.ier().modify(|w| {
|
|
w.set_eoaie(false);
|
|
w.set_mceie(false);
|
|
});
|
|
|
|
// Clear flags
|
|
T::REGS.icr().modify(|w| {
|
|
w.set_eoaic(true);
|
|
w.set_mceic(true);
|
|
});
|
|
|
|
// Set the touch sensing IOs not acquired to the default mode
|
|
T::REGS.cr().modify(|w| {
|
|
w.set_iodef(self.config.io_default_mode);
|
|
});
|
|
|
|
// Start the acquisition
|
|
T::REGS.cr().modify(|w| {
|
|
w.set_start(true);
|
|
});
|
|
}
|
|
|
|
/// Start charge transfer acquisition with interrupts enabled
|
|
pub fn start_it(&mut self) {
|
|
self.state = State::Busy;
|
|
|
|
// Enable interrupts
|
|
T::REGS.ier().modify(|w| {
|
|
w.set_eoaie(true);
|
|
w.set_mceie(self.config.max_count_interrupt);
|
|
});
|
|
|
|
// Clear flags
|
|
T::REGS.icr().modify(|w| {
|
|
w.set_eoaic(true);
|
|
w.set_mceic(true);
|
|
});
|
|
|
|
// Set the touch sensing IOs not acquired to the default mode
|
|
T::REGS.cr().modify(|w| {
|
|
w.set_iodef(self.config.io_default_mode);
|
|
});
|
|
|
|
// Start the acquisition
|
|
T::REGS.cr().modify(|w| {
|
|
w.set_start(true);
|
|
});
|
|
}
|
|
|
|
/// Stop charge transfer acquisition
|
|
pub fn stop(&mut self) {
|
|
T::REGS.cr().modify(|w| {
|
|
w.set_start(false);
|
|
});
|
|
|
|
// Set the touch sensing IOs in low power mode
|
|
T::REGS.cr().modify(|w| {
|
|
w.set_iodef(false);
|
|
});
|
|
|
|
// Clear flags
|
|
T::REGS.icr().modify(|w| {
|
|
w.set_eoaic(true);
|
|
w.set_mceic(true);
|
|
});
|
|
|
|
self.state = State::Ready;
|
|
}
|
|
|
|
/// Stop charge transfer acquisition and clear interrupts
|
|
pub fn stop_it(&mut self) {
|
|
T::REGS.cr().modify(|w| {
|
|
w.set_start(false);
|
|
});
|
|
|
|
// Set the touch sensing IOs in low power mode
|
|
T::REGS.cr().modify(|w| {
|
|
w.set_iodef(false);
|
|
});
|
|
|
|
// Disable interrupts
|
|
T::REGS.ier().modify(|w| {
|
|
w.set_eoaie(false);
|
|
w.set_mceie(false);
|
|
});
|
|
|
|
// Clear flags
|
|
T::REGS.icr().modify(|w| {
|
|
w.set_eoaic(true);
|
|
w.set_mceic(true);
|
|
});
|
|
|
|
self.state = State::Ready;
|
|
}
|
|
|
|
/// Wait for end of acquisition
|
|
pub fn poll_for_acquisition(&mut self) {
|
|
while self.get_state() == State::Busy {}
|
|
}
|
|
|
|
/// Get current state of acquisition
|
|
pub fn get_state(&mut self) -> State {
|
|
if self.state == State::Busy {
|
|
if T::REGS.isr().read().eoaf() {
|
|
if T::REGS.isr().read().mcef() {
|
|
self.state = State::Error
|
|
} else {
|
|
self.state = State::Ready
|
|
}
|
|
}
|
|
}
|
|
self.state
|
|
}
|
|
|
|
/// Get the individual group status to check acquisition complete
|
|
pub fn group_get_status(&mut self, index: Group) -> GroupStatus {
|
|
// Status bits are set by hardware when the acquisition on the corresponding
|
|
// enabled analog IO group is complete, cleared when new acquisition is started
|
|
let status = match index {
|
|
Group::One => T::REGS.iogcsr().read().g1s(),
|
|
Group::Two => T::REGS.iogcsr().read().g2s(),
|
|
Group::Three => T::REGS.iogcsr().read().g3s(),
|
|
Group::Four => T::REGS.iogcsr().read().g4s(),
|
|
Group::Five => T::REGS.iogcsr().read().g5s(),
|
|
Group::Six => T::REGS.iogcsr().read().g6s(),
|
|
#[cfg(any(tsc_v2, tsc_v3))]
|
|
Group::Seven => T::REGS.iogcsr().read().g7s(),
|
|
#[cfg(tsc_v3)]
|
|
Group::Eight => T::REGS.iogcsr().read().g8s(),
|
|
};
|
|
match status {
|
|
true => GroupStatus::Complete,
|
|
false => GroupStatus::Ongoing,
|
|
}
|
|
}
|
|
|
|
/// Get the count for the acquisiton, valid once group status is set
|
|
pub fn group_get_value(&mut self, index: Group) -> u16 {
|
|
T::REGS.iogcr(index.into()).read().cnt()
|
|
}
|
|
|
|
// pub fn configure_io()
|
|
|
|
/// Discharge the IOs for subsequent acquisition
|
|
pub fn discharge_io(&mut self, status: bool) {
|
|
// Set the touch sensing IOs in low power mode
|
|
T::REGS.cr().modify(|w| {
|
|
w.set_iodef(!status);
|
|
});
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> Drop for Tsc<'d, T> {
|
|
fn drop(&mut self) {
|
|
// Need to figure out what to do with the IOs
|
|
T::disable();
|
|
}
|
|
}
|
|
|
|
pub(crate) trait SealedInstance {
|
|
const REGS: Regs;
|
|
}
|
|
|
|
/// TSC instance trait
|
|
#[allow(private_bounds)]
|
|
pub trait Instance: Peripheral<P = Self> + SealedInstance + RccPeripheral {}
|
|
|
|
foreach_peripheral!(
|
|
(tsc, $inst:ident) => {
|
|
impl SealedInstance for peripherals::$inst {
|
|
const REGS: Regs = crate::pac::$inst;
|
|
}
|
|
|
|
impl Instance for peripherals::$inst {}
|
|
};
|
|
);
|
|
|
|
pin_trait!(G1IO1Pin, Instance);
|
|
pin_trait!(G1IO2Pin, Instance);
|
|
pin_trait!(G1IO3Pin, Instance);
|
|
pin_trait!(G1IO4Pin, Instance);
|
|
pin_trait!(G2IO1Pin, Instance);
|
|
pin_trait!(G2IO2Pin, Instance);
|
|
pin_trait!(G2IO3Pin, Instance);
|
|
pin_trait!(G2IO4Pin, Instance);
|
|
pin_trait!(G3IO1Pin, Instance);
|
|
pin_trait!(G3IO2Pin, Instance);
|
|
pin_trait!(G3IO3Pin, Instance);
|
|
pin_trait!(G3IO4Pin, Instance);
|
|
pin_trait!(G4IO1Pin, Instance);
|
|
pin_trait!(G4IO2Pin, Instance);
|
|
pin_trait!(G4IO3Pin, Instance);
|
|
pin_trait!(G4IO4Pin, Instance);
|
|
pin_trait!(G5IO1Pin, Instance);
|
|
pin_trait!(G5IO2Pin, Instance);
|
|
pin_trait!(G5IO3Pin, Instance);
|
|
pin_trait!(G5IO4Pin, Instance);
|
|
pin_trait!(G6IO1Pin, Instance);
|
|
pin_trait!(G6IO2Pin, Instance);
|
|
pin_trait!(G6IO3Pin, Instance);
|
|
pin_trait!(G6IO4Pin, Instance);
|
|
pin_trait!(G7IO1Pin, Instance);
|
|
pin_trait!(G7IO2Pin, Instance);
|
|
pin_trait!(G7IO3Pin, Instance);
|
|
pin_trait!(G7IO4Pin, Instance);
|
|
pin_trait!(G8IO1Pin, Instance);
|
|
pin_trait!(G8IO2Pin, Instance);
|
|
pin_trait!(G8IO3Pin, Instance);
|
|
pin_trait!(G8IO4Pin, Instance);
|