434 lines
13 KiB
Rust
434 lines
13 KiB
Rust
#![no_main]
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#![no_std]
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// Tested on weact stm32h7b0 board + w25q64 spi flash
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use defmt::info;
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use embassy_executor::Spawner;
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use embassy_stm32::gpio::{Level, Output, Speed};
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use embassy_stm32::mode::Blocking;
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use embassy_stm32::ospi::{
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AddressSize, ChipSelectHighTime, DummyCycles, FIFOThresholdLevel, Instance, MemorySize, MemoryType, Ospi,
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OspiWidth, TransferConfig, WrapSize,
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};
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use embassy_stm32::time::Hertz;
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use embassy_stm32::Config;
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use embassy_time::Timer;
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use {defmt_rtt as _, panic_probe as _};
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#[embassy_executor::main]
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async fn main(_spawner: Spawner) {
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// RCC config
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let mut config = Config::default();
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info!("START");
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{
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use embassy_stm32::rcc::*;
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config.rcc.hsi = Some(HSIPrescaler::DIV1);
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config.rcc.csi = true;
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// Needed for USB
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config.rcc.hsi48 = Some(Hsi48Config { sync_from_usb: true });
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// External oscillator 25MHZ
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config.rcc.hse = Some(Hse {
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freq: Hertz(25_000_000),
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mode: HseMode::Oscillator,
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});
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config.rcc.pll1 = Some(Pll {
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source: PllSource::HSE,
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prediv: PllPreDiv::DIV5,
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mul: PllMul::MUL112,
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divp: Some(PllDiv::DIV2),
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divq: Some(PllDiv::DIV2),
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divr: Some(PllDiv::DIV2),
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});
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config.rcc.sys = Sysclk::PLL1_P;
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config.rcc.ahb_pre = AHBPrescaler::DIV2;
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config.rcc.apb1_pre = APBPrescaler::DIV2;
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config.rcc.apb2_pre = APBPrescaler::DIV2;
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config.rcc.apb3_pre = APBPrescaler::DIV2;
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config.rcc.apb4_pre = APBPrescaler::DIV2;
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config.rcc.voltage_scale = VoltageScale::Scale0;
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}
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// Initialize peripherals
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let p = embassy_stm32::init(config);
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let qspi_config = embassy_stm32::ospi::Config {
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fifo_threshold: FIFOThresholdLevel::_16Bytes,
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memory_type: MemoryType::Micron,
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device_size: MemorySize::_8MiB,
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chip_select_high_time: ChipSelectHighTime::_1Cycle,
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free_running_clock: false,
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clock_mode: false,
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wrap_size: WrapSize::None,
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clock_prescaler: 4,
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sample_shifting: true,
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delay_hold_quarter_cycle: false,
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chip_select_boundary: 0,
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delay_block_bypass: true,
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max_transfer: 0,
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refresh: 0,
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};
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let ospi = embassy_stm32::ospi::Ospi::new_blocking_quadspi(
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p.OCTOSPI1,
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p.PB2,
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p.PD11,
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p.PD12,
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p.PE2,
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p.PD13,
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p.PB6,
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qspi_config,
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);
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let mut flash = FlashMemory::new(ospi).await;
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let flash_id = flash.read_id();
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info!("FLASH ID: {=[u8]:x}", flash_id);
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let mut wr_buf = [0u8; 8];
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for i in 0..8 {
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wr_buf[i] = i as u8;
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}
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let mut rd_buf = [0u8; 8];
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flash.erase_sector(0).await;
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flash.write_memory(0, &wr_buf, true).await;
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flash.read_memory(0, &mut rd_buf, true);
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info!("WRITE BUF: {=[u8]:#X}", wr_buf);
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info!("READ BUF: {=[u8]:#X}", rd_buf);
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flash.enable_mm().await;
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info!("Enabled memory mapped mode");
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let first_u32 = unsafe { *(0x90000000 as *const u32) };
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assert_eq!(first_u32, 0x03020100);
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let second_u32 = unsafe { *(0x90000004 as *const u32) };
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assert_eq!(second_u32, 0x07060504);
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flash.disable_mm().await;
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info!("DONE");
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// Output pin PE3
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let mut led = Output::new(p.PE3, Level::Low, Speed::Low);
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loop {
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led.toggle();
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Timer::after_millis(1000).await;
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}
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}
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const MEMORY_PAGE_SIZE: usize = 8;
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const CMD_QUAD_READ: u8 = 0x6B;
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const CMD_QUAD_WRITE_PG: u8 = 0x32;
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const CMD_READ_ID: u8 = 0x9F;
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const CMD_ENABLE_RESET: u8 = 0x66;
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const CMD_RESET: u8 = 0x99;
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const CMD_WRITE_ENABLE: u8 = 0x06;
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const CMD_CHIP_ERASE: u8 = 0xC7;
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const CMD_SECTOR_ERASE: u8 = 0x20;
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const CMD_BLOCK_ERASE_32K: u8 = 0x52;
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const CMD_BLOCK_ERASE_64K: u8 = 0xD8;
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const CMD_READ_SR: u8 = 0x05;
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const CMD_READ_CR: u8 = 0x35;
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const CMD_WRITE_SR: u8 = 0x01;
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const CMD_WRITE_CR: u8 = 0x31;
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/// Implementation of access to flash chip.
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/// Chip commands are hardcoded as it depends on used chip.
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/// This implementation is using chip GD25Q64C from Giga Device
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pub struct FlashMemory<I: Instance> {
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ospi: Ospi<'static, I, Blocking>,
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}
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impl<I: Instance> FlashMemory<I> {
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pub async fn new(ospi: Ospi<'static, I, Blocking>) -> Self {
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let mut memory = Self { ospi };
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memory.reset_memory().await;
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memory.enable_quad();
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memory
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}
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async fn qpi_mode(&mut self) {
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// Enter qpi mode
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self.exec_command(0x38).await;
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// Set read param
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let transaction = TransferConfig {
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iwidth: OspiWidth::QUAD,
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dwidth: OspiWidth::QUAD,
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instruction: Some(0xC0),
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..Default::default()
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};
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self.enable_write().await;
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self.ospi.blocking_write(&[0x30_u8], transaction).unwrap();
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self.wait_write_finish();
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}
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pub async fn disable_mm(&mut self) {
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self.ospi.disable_memory_mapped_mode();
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}
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pub async fn enable_mm(&mut self) {
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self.qpi_mode().await;
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let read_config = TransferConfig {
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iwidth: OspiWidth::QUAD,
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isize: AddressSize::_8Bit,
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adwidth: OspiWidth::QUAD,
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adsize: AddressSize::_24bit,
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dwidth: OspiWidth::QUAD,
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instruction: Some(0x0B), // Fast read in QPI mode
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dummy: DummyCycles::_8,
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..Default::default()
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};
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let write_config = TransferConfig {
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iwidth: OspiWidth::SING,
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isize: AddressSize::_8Bit,
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adwidth: OspiWidth::SING,
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adsize: AddressSize::_24bit,
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dwidth: OspiWidth::QUAD,
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instruction: Some(0x32), // Write config
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dummy: DummyCycles::_0,
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..Default::default()
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};
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self.ospi.enable_memory_mapped_mode(read_config, write_config).unwrap();
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}
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fn enable_quad(&mut self) {
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let cr = self.read_cr();
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// info!("Read cr: {:x}", cr);
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self.write_cr(cr | 0x02);
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// info!("Read cr after writing: {:x}", cr);
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}
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pub fn disable_quad(&mut self) {
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let cr = self.read_cr();
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self.write_cr(cr & (!(0x02)));
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}
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async fn exec_command_4(&mut self, cmd: u8) {
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let transaction = TransferConfig {
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iwidth: OspiWidth::QUAD,
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adwidth: OspiWidth::NONE,
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// adsize: AddressSize::_24bit,
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dwidth: OspiWidth::NONE,
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instruction: Some(cmd as u32),
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address: None,
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dummy: DummyCycles::_0,
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..Default::default()
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};
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self.ospi.blocking_command(&transaction).unwrap();
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}
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async fn exec_command(&mut self, cmd: u8) {
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let transaction = TransferConfig {
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iwidth: OspiWidth::SING,
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adwidth: OspiWidth::NONE,
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// adsize: AddressSize::_24bit,
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dwidth: OspiWidth::NONE,
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instruction: Some(cmd as u32),
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address: None,
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dummy: DummyCycles::_0,
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..Default::default()
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};
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// info!("Excuting command: {:x}", transaction.instruction);
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self.ospi.blocking_command(&transaction).unwrap();
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}
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pub async fn reset_memory(&mut self) {
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self.exec_command_4(CMD_ENABLE_RESET).await;
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self.exec_command_4(CMD_RESET).await;
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self.exec_command(CMD_ENABLE_RESET).await;
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self.exec_command(CMD_RESET).await;
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self.wait_write_finish();
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}
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pub async fn enable_write(&mut self) {
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self.exec_command(CMD_WRITE_ENABLE).await;
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}
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pub fn read_id(&mut self) -> [u8; 3] {
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let mut buffer = [0; 3];
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let transaction: TransferConfig = TransferConfig {
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iwidth: OspiWidth::SING,
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isize: AddressSize::_8Bit,
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adwidth: OspiWidth::NONE,
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// adsize: AddressSize::_24bit,
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dwidth: OspiWidth::SING,
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instruction: Some(CMD_READ_ID as u32),
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..Default::default()
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};
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// info!("Reading id: 0x{:X}", transaction.instruction);
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self.ospi.blocking_read(&mut buffer, transaction).unwrap();
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buffer
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}
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pub fn read_id_4(&mut self) -> [u8; 3] {
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let mut buffer = [0; 3];
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let transaction: TransferConfig = TransferConfig {
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iwidth: OspiWidth::SING,
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isize: AddressSize::_8Bit,
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adwidth: OspiWidth::NONE,
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dwidth: OspiWidth::QUAD,
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instruction: Some(CMD_READ_ID as u32),
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..Default::default()
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};
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info!("Reading id: 0x{:X}", transaction.instruction);
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self.ospi.blocking_read(&mut buffer, transaction).unwrap();
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buffer
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}
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pub fn read_memory(&mut self, addr: u32, buffer: &mut [u8], use_dma: bool) {
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let transaction = TransferConfig {
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iwidth: OspiWidth::SING,
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adwidth: OspiWidth::SING,
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adsize: AddressSize::_24bit,
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dwidth: OspiWidth::QUAD,
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instruction: Some(CMD_QUAD_READ as u32),
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address: Some(addr),
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dummy: DummyCycles::_8,
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..Default::default()
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};
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if use_dma {
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self.ospi.blocking_read(buffer, transaction).unwrap();
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} else {
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self.ospi.blocking_read(buffer, transaction).unwrap();
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}
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}
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fn wait_write_finish(&mut self) {
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while (self.read_sr() & 0x01) != 0 {}
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}
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async fn perform_erase(&mut self, addr: u32, cmd: u8) {
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let transaction = TransferConfig {
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iwidth: OspiWidth::SING,
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adwidth: OspiWidth::SING,
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adsize: AddressSize::_24bit,
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dwidth: OspiWidth::NONE,
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instruction: Some(cmd as u32),
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address: Some(addr),
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dummy: DummyCycles::_0,
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..Default::default()
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};
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self.enable_write().await;
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self.ospi.blocking_command(&transaction).unwrap();
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self.wait_write_finish();
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}
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pub async fn erase_sector(&mut self, addr: u32) {
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self.perform_erase(addr, CMD_SECTOR_ERASE).await;
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}
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pub async fn erase_block_32k(&mut self, addr: u32) {
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self.perform_erase(addr, CMD_BLOCK_ERASE_32K).await;
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}
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pub async fn erase_block_64k(&mut self, addr: u32) {
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self.perform_erase(addr, CMD_BLOCK_ERASE_64K).await;
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}
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pub async fn erase_chip(&mut self) {
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self.exec_command(CMD_CHIP_ERASE).await;
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}
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async fn write_page(&mut self, addr: u32, buffer: &[u8], len: usize, use_dma: bool) {
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assert!(
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(len as u32 + (addr & 0x000000ff)) <= MEMORY_PAGE_SIZE as u32,
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"write_page(): page write length exceeds page boundary (len = {}, addr = {:X}",
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len,
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addr
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);
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let transaction = TransferConfig {
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iwidth: OspiWidth::SING,
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adsize: AddressSize::_24bit,
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adwidth: OspiWidth::SING,
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dwidth: OspiWidth::QUAD,
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instruction: Some(CMD_QUAD_WRITE_PG as u32),
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address: Some(addr),
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dummy: DummyCycles::_0,
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..Default::default()
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};
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self.enable_write().await;
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if use_dma {
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self.ospi.blocking_write(buffer, transaction).unwrap();
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} else {
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self.ospi.blocking_write(buffer, transaction).unwrap();
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}
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self.wait_write_finish();
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}
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pub async fn write_memory(&mut self, addr: u32, buffer: &[u8], use_dma: bool) {
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let mut left = buffer.len();
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let mut place = addr;
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let mut chunk_start = 0;
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while left > 0 {
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let max_chunk_size = MEMORY_PAGE_SIZE - (place & 0x000000ff) as usize;
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let chunk_size = if left >= max_chunk_size { max_chunk_size } else { left };
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let chunk = &buffer[chunk_start..(chunk_start + chunk_size)];
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self.write_page(place, chunk, chunk_size, use_dma).await;
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place += chunk_size as u32;
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left -= chunk_size;
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chunk_start += chunk_size;
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}
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}
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fn read_register(&mut self, cmd: u8) -> u8 {
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let mut buffer = [0; 1];
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let transaction: TransferConfig = TransferConfig {
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iwidth: OspiWidth::SING,
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isize: AddressSize::_8Bit,
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adwidth: OspiWidth::NONE,
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adsize: AddressSize::_24bit,
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dwidth: OspiWidth::SING,
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instruction: Some(cmd as u32),
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address: None,
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dummy: DummyCycles::_0,
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..Default::default()
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};
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self.ospi.blocking_read(&mut buffer, transaction).unwrap();
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// info!("Read w25q64 register: 0x{:x}", buffer[0]);
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buffer[0]
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}
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fn write_register(&mut self, cmd: u8, value: u8) {
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let buffer = [value; 1];
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let transaction: TransferConfig = TransferConfig {
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iwidth: OspiWidth::SING,
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isize: AddressSize::_8Bit,
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instruction: Some(cmd as u32),
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adsize: AddressSize::_24bit,
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adwidth: OspiWidth::NONE,
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dwidth: OspiWidth::SING,
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address: None,
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dummy: DummyCycles::_0,
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..Default::default()
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};
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self.ospi.blocking_write(&buffer, transaction).unwrap();
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}
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pub fn read_sr(&mut self) -> u8 {
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self.read_register(CMD_READ_SR)
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}
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pub fn read_cr(&mut self) -> u8 {
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self.read_register(CMD_READ_CR)
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}
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pub fn write_sr(&mut self, value: u8) {
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self.write_register(CMD_WRITE_SR, value);
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}
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pub fn write_cr(&mut self, value: u8) {
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self.write_register(CMD_WRITE_CR, value);
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}
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}
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