401 lines
11 KiB
Rust
401 lines
11 KiB
Rust
#![macro_use]
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use core::future::Future;
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use core::marker::PhantomData;
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use core::task::Poll;
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use embassy::interrupt::{Interrupt, InterruptExt};
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use embassy::traits::flash::{Error, Flash};
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use embassy::util::{AtomicWaker, DropBomb, Unborrow};
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use embassy_extras::unborrow;
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use futures::future::poll_fn;
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use crate::fmt::{assert, assert_eq, *};
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use crate::gpio::Pin as GpioPin;
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use crate::pac;
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pub use crate::pac::qspi::ifconfig0::ADDRMODE_A as AddressMode;
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pub use crate::pac::qspi::ifconfig0::PPSIZE_A as WritePageSize;
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pub use crate::pac::qspi::ifconfig0::READOC_A as ReadOpcode;
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pub use crate::pac::qspi::ifconfig0::WRITEOC_A as WriteOpcode;
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// TODO
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// - config:
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// - 32bit address mode
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// - SPI freq
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// - SPI sck delay
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// - Deep power down mode (DPM)
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// - SPI mode 3
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// - activate/deactivate
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// - set gpio in high drive
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pub struct DeepPowerDownConfig {
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pub enter_time: u16,
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pub exit_time: u16,
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}
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#[non_exhaustive]
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pub struct Config {
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pub xip_offset: u32,
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pub read_opcode: ReadOpcode,
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pub write_opcode: WriteOpcode,
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pub write_page_size: WritePageSize,
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pub deep_power_down: Option<DeepPowerDownConfig>,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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read_opcode: ReadOpcode::READ4IO,
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write_opcode: WriteOpcode::PP4IO,
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xip_offset: 0,
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write_page_size: WritePageSize::_256BYTES,
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deep_power_down: None,
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}
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}
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}
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pub struct Qspi<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Instance> Qspi<'d, T> {
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pub fn new(
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_qspi: impl Unborrow<Target = T> + 'd,
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irq: impl Unborrow<Target = T::Interrupt> + 'd,
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sck: impl Unborrow<Target = impl GpioPin> + 'd,
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csn: impl Unborrow<Target = impl GpioPin> + 'd,
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io0: impl Unborrow<Target = impl GpioPin> + 'd,
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io1: impl Unborrow<Target = impl GpioPin> + 'd,
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io2: impl Unborrow<Target = impl GpioPin> + 'd,
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io3: impl Unborrow<Target = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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unborrow!(irq, sck, csn, io0, io1, io2, io3);
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let r = T::regs();
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for cnf in &[
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sck.conf(),
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csn.conf(),
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io0.conf(),
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io1.conf(),
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io2.conf(),
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io3.conf(),
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] {
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cnf.write(|w| w.dir().output().drive().h0h1());
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}
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r.psel.sck.write(|w| unsafe { w.bits(sck.psel_bits()) });
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r.psel.csn.write(|w| unsafe { w.bits(csn.psel_bits()) });
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r.psel.io0.write(|w| unsafe { w.bits(io0.psel_bits()) });
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r.psel.io1.write(|w| unsafe { w.bits(io1.psel_bits()) });
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r.psel.io2.write(|w| unsafe { w.bits(io2.psel_bits()) });
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r.psel.io3.write(|w| unsafe { w.bits(io3.psel_bits()) });
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r.ifconfig0.write(|mut w| {
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w = w.addrmode().variant(AddressMode::_24BIT);
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if config.deep_power_down.is_some() {
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w = w.dpmenable().enable();
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} else {
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w = w.dpmenable().disable();
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}
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w = w.ppsize().variant(config.write_page_size);
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w = w.readoc().variant(config.read_opcode);
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w = w.writeoc().variant(config.write_opcode);
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w
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});
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if let Some(dpd) = &config.deep_power_down {
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r.dpmdur.write(|mut w| unsafe {
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w = w.enter().bits(dpd.enter_time);
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w = w.exit().bits(dpd.exit_time);
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w
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})
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}
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r.ifconfig1.write(|w| {
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let w = unsafe { w.sckdelay().bits(80) };
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let w = w.dpmen().exit();
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let w = w.spimode().mode0();
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let w = unsafe { w.sckfreq().bits(3) };
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w
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});
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r.xipoffset
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.write(|w| unsafe { w.xipoffset().bits(config.xip_offset) });
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// Enable it
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r.enable.write(|w| w.enable().enabled());
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r.events_ready.reset();
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r.tasks_activate.write(|w| w.tasks_activate().bit(true));
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while r.events_ready.read().bits() == 0 {}
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r.events_ready.reset();
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irq.set_handler(Self::on_interrupt);
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irq.unpend();
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irq.enable();
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Self {
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phantom: PhantomData,
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}
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}
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fn on_interrupt(_: *mut ()) {
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let r = T::regs();
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let s = T::state();
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if r.events_ready.read().bits() != 0 {
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s.ready_waker.wake();
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r.intenclr.write(|w| w.ready().clear());
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}
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}
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pub fn sleep(&mut self) {
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let r = T::regs();
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info!("flash: sleeping");
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info!("flash: state = {:?}", r.status.read().bits());
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r.ifconfig1.modify(|_, w| w.dpmen().enter());
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info!("flash: state = {:?}", r.status.read().bits());
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cortex_m::asm::delay(1000000);
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info!("flash: state = {:?}", r.status.read().bits());
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r.tasks_deactivate.write(|w| w.tasks_deactivate().set_bit());
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}
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pub async fn custom_instruction(
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&mut self,
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opcode: u8,
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req: &[u8],
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resp: &mut [u8],
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) -> Result<(), Error> {
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let bomb = DropBomb::new();
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assert!(req.len() <= 8);
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assert!(resp.len() <= 8);
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let mut dat0: u32 = 0;
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let mut dat1: u32 = 0;
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for i in 0..4 {
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if i < req.len() {
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dat0 |= (req[i] as u32) << (i * 8);
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}
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}
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for i in 0..4 {
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if i + 4 < req.len() {
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dat1 |= (req[i + 4] as u32) << (i * 8);
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}
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}
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let len = core::cmp::max(req.len(), resp.len()) as u8;
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let r = T::regs();
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r.cinstrdat0.write(|w| unsafe { w.bits(dat0) });
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r.cinstrdat1.write(|w| unsafe { w.bits(dat1) });
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r.events_ready.reset();
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r.intenset.write(|w| w.ready().set());
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r.cinstrconf.write(|w| {
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let w = unsafe { w.opcode().bits(opcode) };
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let w = unsafe { w.length().bits(len + 1) };
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let w = w.lio2().bit(true);
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let w = w.lio3().bit(true);
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let w = w.wipwait().bit(true);
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let w = w.wren().bit(true);
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let w = w.lfen().bit(false);
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let w = w.lfstop().bit(false);
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w
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});
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self.wait_ready().await;
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let r = T::regs();
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let dat0 = r.cinstrdat0.read().bits();
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let dat1 = r.cinstrdat1.read().bits();
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for i in 0..4 {
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if i < resp.len() {
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resp[i] = (dat0 >> (i * 8)) as u8;
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}
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}
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for i in 0..4 {
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if i + 4 < resp.len() {
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resp[i] = (dat1 >> (i * 8)) as u8;
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}
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}
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bomb.defuse();
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Ok(())
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}
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async fn wait_ready(&mut self) {
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poll_fn(move |cx| {
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let r = T::regs();
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let s = T::state();
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s.ready_waker.register(cx.waker());
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if r.events_ready.read().bits() != 0 {
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return Poll::Ready(());
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}
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Poll::Pending
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})
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.await
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}
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}
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impl<'d, T: Instance> Flash for Qspi<'d, T> {
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#[rustfmt::skip]
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type ReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Error>> + 'a;
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#[rustfmt::skip]
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type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), Error>> + 'a;
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#[rustfmt::skip]
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type ErasePageFuture<'a> where Self: 'a = impl Future<Output = Result<(), Error>> + 'a;
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fn read<'a>(&'a mut self, address: usize, data: &'a mut [u8]) -> Self::ReadFuture<'a> {
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async move {
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let bomb = DropBomb::new();
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assert_eq!(data.as_ptr() as u32 % 4, 0);
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assert_eq!(data.len() as u32 % 4, 0);
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assert_eq!(address as u32 % 4, 0);
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let r = T::regs();
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r.read
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.src
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.write(|w| unsafe { w.src().bits(address as u32) });
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r.read
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.dst
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.write(|w| unsafe { w.dst().bits(data.as_ptr() as u32) });
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r.read
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.cnt
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.write(|w| unsafe { w.cnt().bits(data.len() as u32) });
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r.events_ready.reset();
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r.intenset.write(|w| w.ready().set());
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r.tasks_readstart.write(|w| w.tasks_readstart().bit(true));
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self.wait_ready().await;
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bomb.defuse();
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Ok(())
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}
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}
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fn write<'a>(&'a mut self, address: usize, data: &'a [u8]) -> Self::WriteFuture<'a> {
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async move {
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let bomb = DropBomb::new();
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assert_eq!(data.as_ptr() as u32 % 4, 0);
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assert_eq!(data.len() as u32 % 4, 0);
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assert_eq!(address as u32 % 4, 0);
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let r = T::regs();
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r.write
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.src
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.write(|w| unsafe { w.src().bits(data.as_ptr() as u32) });
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r.write
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.dst
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.write(|w| unsafe { w.dst().bits(address as u32) });
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r.write
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.cnt
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.write(|w| unsafe { w.cnt().bits(data.len() as u32) });
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r.events_ready.reset();
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r.intenset.write(|w| w.ready().set());
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r.tasks_writestart.write(|w| w.tasks_writestart().bit(true));
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self.wait_ready().await;
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bomb.defuse();
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Ok(())
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}
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}
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fn erase<'a>(&'a mut self, address: usize) -> Self::ErasePageFuture<'a> {
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async move {
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let bomb = DropBomb::new();
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assert_eq!(address as u32 % 4096, 0);
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let r = T::regs();
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r.erase
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.ptr
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.write(|w| unsafe { w.ptr().bits(address as u32) });
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r.erase.len.write(|w| w.len()._4kb());
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r.events_ready.reset();
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r.intenset.write(|w| w.ready().set());
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r.tasks_erasestart.write(|w| w.tasks_erasestart().bit(true));
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self.wait_ready().await;
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bomb.defuse();
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Ok(())
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}
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}
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fn size(&self) -> usize {
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256 * 4096 // TODO
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}
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fn read_size(&self) -> usize {
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4 // TODO
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}
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fn write_size(&self) -> usize {
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4 // TODO
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}
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fn erase_size(&self) -> usize {
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4096 // TODO
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}
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}
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pub(crate) mod sealed {
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use super::*;
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pub struct State {
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pub ready_waker: AtomicWaker,
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}
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impl State {
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pub const fn new() -> Self {
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Self {
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ready_waker: AtomicWaker::new(),
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}
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}
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}
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pub trait Instance {
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fn regs() -> &'static pac::qspi::RegisterBlock;
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fn state() -> &'static State;
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}
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}
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pub trait Instance: Unborrow<Target = Self> + sealed::Instance + 'static {
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type Interrupt: Interrupt;
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}
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macro_rules! impl_qspi {
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($type:ident, $pac_type:ident, $irq:ident) => {
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impl crate::qspi::sealed::Instance for peripherals::$type {
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fn regs() -> &'static pac::qspi::RegisterBlock {
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unsafe { &*pac::$pac_type::ptr() }
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}
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fn state() -> &'static crate::qspi::sealed::State {
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static STATE: crate::qspi::sealed::State = crate::qspi::sealed::State::new();
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&STATE
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}
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}
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impl crate::qspi::Instance for peripherals::$type {
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type Interrupt = crate::interrupt::$irq;
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}
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};
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}
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