359 lines
11 KiB
Rust
359 lines
11 KiB
Rust
use crate::pac::flash::vals::Latency;
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pub use crate::pac::rcc::vals::{
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Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv,
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Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
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};
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use crate::pac::{FLASH, PWR, RCC};
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use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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/// HSE Mode
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub enum HseMode {
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/// crystal/ceramic oscillator (HSEBYP=0)
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Oscillator,
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/// external analog clock (low swing) (HSEBYP=1)
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Bypass,
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}
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/// HSE Configuration
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub struct Hse {
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/// HSE frequency.
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pub freq: Hertz,
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/// HSE mode.
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pub mode: HseMode,
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}
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/// PLL Configuration
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///
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/// Use this struct to configure the PLL source, input frequency, multiplication factor, and output
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/// dividers. Be sure to keep check the datasheet for your specific part for the appropriate
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/// frequency ranges for each of these settings.
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#[derive(Clone, Copy)]
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pub struct Pll {
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/// PLL Source clock selection.
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pub source: PllSource,
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/// PLL pre-divider
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pub prediv: PllPreDiv,
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/// PLL multiplication factor for VCO
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pub mul: PllMul,
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/// PLL division factor for P clock (ADC Clock)
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pub divp: Option<PllPDiv>,
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/// PLL division factor for Q clock (USB, I2S23, SAI1, FDCAN, QSPI)
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pub divq: Option<PllQDiv>,
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/// PLL division factor for R clock (SYSCLK)
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pub divr: Option<PllRDiv>,
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}
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/// Clocks configutation
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#[non_exhaustive]
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#[derive(Clone, Copy)]
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pub struct Config {
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/// HSI Enable
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pub hsi: bool,
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/// HSE Configuration
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pub hse: Option<Hse>,
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/// System Clock Configuration
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pub sys: Sysclk,
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/// HSI48 Configuration
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pub hsi48: Option<super::Hsi48Config>,
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/// PLL Configuration
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pub pll: Option<Pll>,
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/// If PLL is requested as the main clock source in the `sys` field then the PLL configuration
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/// MUST turn on the PLLR output.
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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pub low_power_run: bool,
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/// Low-Speed Clock Configuration
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pub ls: super::LsConfig,
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/// Enable range1 boost mode
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/// Recommended when the SYSCLK frequency is greater than 150MHz.
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pub boost: bool,
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/// Per-peripheral kernel clock selection muxes
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pub mux: super::mux::ClockMux,
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}
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impl Default for Config {
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#[inline]
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fn default() -> Config {
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Config {
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hsi: true,
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hse: None,
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sys: Sysclk::HSI,
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hsi48: Some(Default::default()),
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pll: None,
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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apb2_pre: APBPrescaler::DIV1,
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low_power_run: false,
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ls: Default::default(),
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boost: false,
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mux: Default::default(),
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}
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}
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}
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#[derive(Default)]
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pub struct PllFreq {
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pub pll_p: Option<Hertz>,
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pub pll_q: Option<Hertz>,
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pub pll_r: Option<Hertz>,
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}
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pub(crate) unsafe fn init(config: Config) {
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// Turn on the HSI
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RCC.cr().modify(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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// Use the HSI clock as system clock during the actual clock setup
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RCC.cfgr().modify(|w| w.set_sw(Sysclk::HSI));
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while RCC.cfgr().read().sws() != Sysclk::HSI {}
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// Configure HSI
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let hsi = match config.hsi {
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false => None,
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true => Some(HSI_FREQ),
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};
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// Configure HSE
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let hse = match config.hse {
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None => {
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RCC.cr().modify(|w| w.set_hseon(false));
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None
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}
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Some(hse) => {
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match hse.mode {
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HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
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HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
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}
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RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
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RCC.cr().modify(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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Some(hse.freq)
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}
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};
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// Configure HSI48 if required
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let hsi48 = config.hsi48.map(super::init_hsi48);
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let pll = config
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.pll
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.map(|pll_config| {
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let src_freq = match pll_config.source {
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PllSource::HSI => unwrap!(hsi),
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PllSource::HSE => unwrap!(hse),
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_ => unreachable!(),
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};
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// Disable PLL before configuration
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RCC.cr().modify(|w| w.set_pllon(false));
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while RCC.cr().read().pllrdy() {}
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let in_freq = src_freq / pll_config.prediv;
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rcc_assert!(max::PLL_IN.contains(&in_freq));
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let internal_freq = in_freq * pll_config.mul;
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rcc_assert!(max::PLL_VCO.contains(&internal_freq));
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RCC.pllcfgr().write(|w| {
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w.set_plln(pll_config.mul);
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w.set_pllm(pll_config.prediv);
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w.set_pllsrc(pll_config.source.into());
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});
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let pll_p_freq = pll_config.divp.map(|div_p| {
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RCC.pllcfgr().modify(|w| {
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w.set_pllp(div_p);
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w.set_pllpen(true);
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});
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let freq = internal_freq / div_p;
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rcc_assert!(max::PLL_P.contains(&freq));
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freq
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});
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let pll_q_freq = pll_config.divq.map(|div_q| {
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RCC.pllcfgr().modify(|w| {
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w.set_pllq(div_q);
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w.set_pllqen(true);
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});
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let freq = internal_freq / div_q;
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rcc_assert!(max::PLL_Q.contains(&freq));
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freq
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});
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let pll_r_freq = pll_config.divr.map(|div_r| {
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RCC.pllcfgr().modify(|w| {
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w.set_pllr(div_r);
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w.set_pllren(true);
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});
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let freq = internal_freq / div_r;
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rcc_assert!(max::PLL_R.contains(&freq));
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freq
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});
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// Enable the PLL
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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PllFreq {
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pll_p: pll_p_freq,
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pll_q: pll_q_freq,
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pll_r: pll_r_freq,
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}
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})
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.unwrap_or_default();
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let sys = match config.sys {
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Sysclk::HSI => unwrap!(hsi),
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Sysclk::HSE => unwrap!(hse),
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Sysclk::PLL1_R => unwrap!(pll.pll_r),
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_ => unreachable!(),
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};
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rcc_assert!(max::SYSCLK.contains(&sys));
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// Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
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let hclk = sys / config.ahb_pre;
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rcc_assert!(max::HCLK.contains(&hclk));
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let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
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let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
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rcc_assert!(max::PCLK.contains(&pclk1));
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rcc_assert!(max::PCLK.contains(&pclk2));
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// Configure Core Boost mode ([RM0440] p234 – inverted because setting r1mode to 0 enables boost mode!)
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if config.boost {
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// RM0440 p235
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// “The sequence to switch from Range1 normal mode to Range1 boost mode is:
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// 1. The system clock must be divided by 2 using the AHB prescaler before switching to a higher system frequency.
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RCC.cfgr().modify(|w| w.set_hpre(AHBPrescaler::DIV2));
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// 2. Clear the R1MODE bit in the PWR_CR5 register. (enables boost mode)
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PWR.cr5().modify(|w| w.set_r1mode(false));
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// Below:
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// 3. Adjust wait states according to new freq target
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// 4. Configure and switch to new frequency
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}
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let latency = match (config.boost, hclk.0) {
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(true, ..=34_000_000) => Latency::WS0,
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(true, ..=68_000_000) => Latency::WS1,
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(true, ..=102_000_000) => Latency::WS2,
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(true, ..=136_000_000) => Latency::WS3,
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(true, _) => Latency::WS4,
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(false, ..=36_000_000) => Latency::WS0,
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(false, ..=60_000_000) => Latency::WS1,
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(false, ..=90_000_000) => Latency::WS2,
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(false, ..=120_000_000) => Latency::WS3,
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(false, _) => Latency::WS4,
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};
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// Configure flash read access latency based on boost mode and frequency (RM0440 p98)
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FLASH.acr().modify(|w| {
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w.set_latency(latency);
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});
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// Spin until the effective flash latency is set.
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while FLASH.acr().read().latency() != latency {}
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if config.boost {
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// 5. Wait for at least 1us and then reconfigure the AHB prescaler to get the needed HCLK clock frequency.
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cortex_m::asm::delay(16);
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}
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// Now that boost mode and flash read access latency are configured, set up SYSCLK
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RCC.cfgr().modify(|w| {
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w.set_sw(config.sys);
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w.set_hpre(config.ahb_pre);
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w.set_ppre1(config.apb1_pre);
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w.set_ppre2(config.apb2_pre);
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});
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while RCC.cfgr().read().sws() != config.sys {}
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// Disable HSI if not used
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if !config.hsi {
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RCC.cr().modify(|w| w.set_hsion(false));
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}
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if config.low_power_run {
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assert!(sys <= Hertz(2_000_000));
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PWR.cr1().modify(|w| w.set_lpr(true));
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}
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let rtc = config.ls.init();
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config.mux.init();
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set_clocks!(
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sys: Some(sys),
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hclk1: Some(hclk),
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hclk2: Some(hclk),
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hclk3: Some(hclk),
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pclk1: Some(pclk1),
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pclk1_tim: Some(pclk1_tim),
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pclk2: Some(pclk2),
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pclk2_tim: Some(pclk2_tim),
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pll1_p: pll.pll_p,
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pll1_q: pll.pll_q,
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pll1_r: pll.pll_r,
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hsi: hsi,
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hse: hse,
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hsi48: hsi48,
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rtc: rtc,
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);
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}
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/// Acceptable Frequency Ranges
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/// Currently assuming voltage scaling range 1 boost mode.
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/// Where not specified in the generic G4 reference manual (RM0440), values taken from the STM32G474 datasheet.
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/// If acceptable ranges for other G4-family chips differ, make additional max modules gated behind cfg attrs.
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mod max {
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use core::ops::RangeInclusive;
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use crate::time::Hertz;
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/// HSE Frequency Range (RM0440 p280)
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pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(48_000_000);
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/// External Clock Frequency Range (RM0440 p280)
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pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(0)..=Hertz(48_000_000);
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/// SYSCLK Frequency Range (RM0440 p282)
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pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(170_000_000);
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/// PLL Output Frequency Range (RM0440 p281, STM32G474 Datasheet p123, Table 46)
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pub(crate) const PCLK: RangeInclusive<Hertz> = Hertz(8)..=Hertz(170_000_000);
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/// HCLK (AHB) Clock Frequency Range (STM32G474 Datasheet)
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pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(170_000_000);
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/// PLL Source Frequency Range (STM32G474 Datasheet p123, Table 46)
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pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(2_660_000)..=Hertz(16_000_000);
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/// PLL VCO (internal) Frequency Range (STM32G474 Datasheet p123, Table 46)
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pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(96_000_000)..=Hertz(344_000_000);
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pub(crate) const PLL_P: RangeInclusive<Hertz> = Hertz(2_064_500)..=Hertz(170_000_000);
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pub(crate) const PLL_Q: RangeInclusive<Hertz> = Hertz(8_000_000)..=Hertz(170_000_000);
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pub(crate) const PLL_R: RangeInclusive<Hertz> = Hertz(8_000_000)..=Hertz(170_000_000);
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}
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