4cc5ab9474
rp235x firmwares need an Image Definition if they want to be called from the rp235x bootrom. Currently this Image Definition is manually added to each project/example, but for most users it will always be the default (Secure Exe). This commit adds crate features to allow users to configure this, with the default of including a Secure Exe Image Definition in. Just like the boot2-* features, this includes an opt-out (imagedef-none) to allow the user to not make use of this included Image Definition.
760 lines
18 KiB
Rust
760 lines
18 KiB
Rust
#![no_std]
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#![allow(async_fn_in_trait)]
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#![doc = include_str!("../README.md")]
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#![warn(missing_docs)]
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//! ## Feature flags
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#![doc = document_features::document_features!(feature_label = r#"<span class="stab portability"><code>{feature}</code></span>"#)]
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// This mod MUST go first, so that the others see its macros.
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pub(crate) mod fmt;
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#[cfg(feature = "binary-info")]
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pub use rp_binary_info as binary_info;
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#[cfg(feature = "critical-section-impl")]
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mod critical_section_impl;
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#[cfg(feature = "rp2040")]
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mod intrinsics;
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pub mod adc;
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#[cfg(feature = "_rp235x")]
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pub mod block;
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#[cfg(feature = "rp2040")]
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pub mod bootsel;
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pub mod clocks;
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pub mod dma;
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pub mod flash;
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#[cfg(feature = "rp2040")]
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mod float;
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pub mod gpio;
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pub mod i2c;
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pub mod i2c_slave;
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pub mod multicore;
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#[cfg(feature = "_rp235x")]
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pub mod otp;
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pub mod pio_programs;
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pub mod pwm;
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mod reset;
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pub mod rom_data;
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#[cfg(feature = "rp2040")]
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pub mod rtc;
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pub mod spi;
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#[cfg(feature = "time-driver")]
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pub mod time_driver;
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#[cfg(feature = "_rp235x")]
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pub mod trng;
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pub mod uart;
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pub mod usb;
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pub mod watchdog;
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// PIO
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pub mod pio;
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pub(crate) mod relocate;
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// Reexports
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pub use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
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#[cfg(feature = "unstable-pac")]
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pub use rp_pac as pac;
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#[cfg(not(feature = "unstable-pac"))]
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pub(crate) use rp_pac as pac;
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#[cfg(feature = "rt")]
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pub use crate::pac::NVIC_PRIO_BITS;
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#[cfg(feature = "rp2040")]
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embassy_hal_internal::interrupt_mod!(
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TIMER_IRQ_0,
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TIMER_IRQ_1,
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TIMER_IRQ_2,
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TIMER_IRQ_3,
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PWM_IRQ_WRAP,
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USBCTRL_IRQ,
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XIP_IRQ,
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PIO0_IRQ_0,
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PIO0_IRQ_1,
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PIO1_IRQ_0,
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PIO1_IRQ_1,
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DMA_IRQ_0,
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DMA_IRQ_1,
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IO_IRQ_BANK0,
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IO_IRQ_QSPI,
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SIO_IRQ_PROC0,
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SIO_IRQ_PROC1,
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CLOCKS_IRQ,
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SPI0_IRQ,
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SPI1_IRQ,
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UART0_IRQ,
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UART1_IRQ,
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ADC_IRQ_FIFO,
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I2C0_IRQ,
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I2C1_IRQ,
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RTC_IRQ,
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SWI_IRQ_0,
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SWI_IRQ_1,
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SWI_IRQ_2,
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SWI_IRQ_3,
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SWI_IRQ_4,
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SWI_IRQ_5,
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);
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#[cfg(feature = "_rp235x")]
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embassy_hal_internal::interrupt_mod!(
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TIMER0_IRQ_0,
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TIMER0_IRQ_1,
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TIMER0_IRQ_2,
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TIMER0_IRQ_3,
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TIMER1_IRQ_0,
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TIMER1_IRQ_1,
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TIMER1_IRQ_2,
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TIMER1_IRQ_3,
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PWM_IRQ_WRAP_0,
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PWM_IRQ_WRAP_1,
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DMA_IRQ_0,
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DMA_IRQ_1,
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USBCTRL_IRQ,
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PIO0_IRQ_0,
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PIO0_IRQ_1,
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PIO1_IRQ_0,
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PIO1_IRQ_1,
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PIO2_IRQ_0,
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PIO2_IRQ_1,
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IO_IRQ_BANK0,
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IO_IRQ_BANK0_NS,
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IO_IRQ_QSPI,
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IO_IRQ_QSPI_NS,
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SIO_IRQ_FIFO,
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SIO_IRQ_BELL,
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SIO_IRQ_FIFO_NS,
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SIO_IRQ_BELL_NS,
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CLOCKS_IRQ,
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SPI0_IRQ,
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SPI1_IRQ,
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UART0_IRQ,
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UART1_IRQ,
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ADC_IRQ_FIFO,
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I2C0_IRQ,
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I2C1_IRQ,
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TRNG_IRQ,
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PLL_SYS_IRQ,
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PLL_USB_IRQ,
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SWI_IRQ_0,
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SWI_IRQ_1,
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SWI_IRQ_2,
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SWI_IRQ_3,
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SWI_IRQ_4,
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SWI_IRQ_5,
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);
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/// Macro to bind interrupts to handlers.
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///
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/// This defines the right interrupt handlers, and creates a unit struct (like `struct Irqs;`)
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/// and implements the right [`Binding`]s for it. You can pass this struct to drivers to
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/// prove at compile-time that the right interrupts have been bound.
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///
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/// Example of how to bind one interrupt:
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///
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/// ```rust,ignore
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/// use embassy_rp::{bind_interrupts, usb, peripherals};
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///
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/// bind_interrupts!(struct Irqs {
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/// USBCTRL_IRQ => usb::InterruptHandler<peripherals::USB>;
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/// });
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/// ```
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///
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// developer note: this macro can't be in `embassy-hal-internal` due to the use of `$crate`.
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#[macro_export]
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macro_rules! bind_interrupts {
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($vis:vis struct $name:ident {
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$(
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$(#[cfg($cond_irq:meta)])?
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$irq:ident => $(
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$(#[cfg($cond_handler:meta)])?
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$handler:ty
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),*;
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)*
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}) => {
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#[derive(Copy, Clone)]
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$vis struct $name;
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$(
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#[allow(non_snake_case)]
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#[no_mangle]
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$(#[cfg($cond_irq)])?
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unsafe extern "C" fn $irq() {
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$(
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$(#[cfg($cond_handler)])?
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<$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt();
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)*
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}
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$(#[cfg($cond_irq)])?
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$crate::bind_interrupts!(@inner
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$(
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$(#[cfg($cond_handler)])?
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unsafe impl $crate::interrupt::typelevel::Binding<$crate::interrupt::typelevel::$irq, $handler> for $name {}
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)*
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);
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)*
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};
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(@inner $($t:tt)*) => {
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$($t)*
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}
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}
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#[cfg(feature = "rp2040")]
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embassy_hal_internal::peripherals! {
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PIN_0,
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PIN_1,
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PIN_2,
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PIN_3,
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PIN_4,
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PIN_5,
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PIN_6,
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PIN_7,
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PIN_8,
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PIN_9,
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PIN_10,
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PIN_11,
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PIN_12,
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PIN_13,
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PIN_14,
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PIN_15,
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PIN_16,
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PIN_17,
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PIN_18,
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PIN_19,
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PIN_20,
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PIN_21,
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PIN_22,
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PIN_23,
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PIN_24,
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PIN_25,
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PIN_26,
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PIN_27,
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PIN_28,
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PIN_29,
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PIN_QSPI_SCLK,
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PIN_QSPI_SS,
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PIN_QSPI_SD0,
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PIN_QSPI_SD1,
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PIN_QSPI_SD2,
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PIN_QSPI_SD3,
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UART0,
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UART1,
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SPI0,
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SPI1,
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I2C0,
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I2C1,
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DMA_CH0,
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DMA_CH1,
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DMA_CH2,
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DMA_CH3,
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DMA_CH4,
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DMA_CH5,
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DMA_CH6,
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DMA_CH7,
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DMA_CH8,
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DMA_CH9,
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DMA_CH10,
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DMA_CH11,
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PWM_SLICE0,
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PWM_SLICE1,
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PWM_SLICE2,
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PWM_SLICE3,
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PWM_SLICE4,
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PWM_SLICE5,
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PWM_SLICE6,
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PWM_SLICE7,
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USB,
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RTC,
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FLASH,
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ADC,
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ADC_TEMP_SENSOR,
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CORE1,
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PIO0,
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PIO1,
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WATCHDOG,
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BOOTSEL,
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}
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#[cfg(feature = "_rp235x")]
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embassy_hal_internal::peripherals! {
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PIN_0,
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PIN_1,
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PIN_2,
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PIN_3,
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PIN_4,
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PIN_5,
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PIN_6,
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PIN_7,
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PIN_8,
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PIN_9,
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PIN_10,
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PIN_11,
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PIN_12,
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PIN_13,
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PIN_14,
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PIN_15,
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PIN_16,
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PIN_17,
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PIN_18,
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PIN_19,
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PIN_20,
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PIN_21,
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PIN_22,
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PIN_23,
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PIN_24,
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PIN_25,
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PIN_26,
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PIN_27,
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PIN_28,
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PIN_29,
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#[cfg(feature = "rp235xb")]
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PIN_30,
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#[cfg(feature = "rp235xb")]
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PIN_31,
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#[cfg(feature = "rp235xb")]
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PIN_32,
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#[cfg(feature = "rp235xb")]
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PIN_33,
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#[cfg(feature = "rp235xb")]
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PIN_34,
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#[cfg(feature = "rp235xb")]
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PIN_35,
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#[cfg(feature = "rp235xb")]
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PIN_36,
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#[cfg(feature = "rp235xb")]
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PIN_37,
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#[cfg(feature = "rp235xb")]
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PIN_38,
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#[cfg(feature = "rp235xb")]
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PIN_39,
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#[cfg(feature = "rp235xb")]
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PIN_40,
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#[cfg(feature = "rp235xb")]
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PIN_41,
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#[cfg(feature = "rp235xb")]
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PIN_42,
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#[cfg(feature = "rp235xb")]
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PIN_43,
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#[cfg(feature = "rp235xb")]
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PIN_44,
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#[cfg(feature = "rp235xb")]
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PIN_45,
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#[cfg(feature = "rp235xb")]
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PIN_46,
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#[cfg(feature = "rp235xb")]
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PIN_47,
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PIN_QSPI_SCLK,
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PIN_QSPI_SS,
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PIN_QSPI_SD0,
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PIN_QSPI_SD1,
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PIN_QSPI_SD2,
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PIN_QSPI_SD3,
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UART0,
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UART1,
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SPI0,
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SPI1,
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I2C0,
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I2C1,
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DMA_CH0,
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DMA_CH1,
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DMA_CH2,
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DMA_CH3,
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DMA_CH4,
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DMA_CH5,
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DMA_CH6,
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DMA_CH7,
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DMA_CH8,
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DMA_CH9,
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DMA_CH10,
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DMA_CH11,
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DMA_CH12,
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DMA_CH13,
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DMA_CH14,
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DMA_CH15,
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PWM_SLICE0,
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PWM_SLICE1,
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PWM_SLICE2,
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PWM_SLICE3,
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PWM_SLICE4,
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PWM_SLICE5,
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PWM_SLICE6,
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PWM_SLICE7,
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PWM_SLICE8,
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PWM_SLICE9,
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PWM_SLICE10,
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PWM_SLICE11,
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USB,
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RTC,
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FLASH,
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ADC,
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ADC_TEMP_SENSOR,
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CORE1,
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PIO0,
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PIO1,
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PIO2,
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WATCHDOG,
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BOOTSEL,
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TRNG
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}
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#[cfg(all(not(feature = "boot2-none"), feature = "rp2040"))]
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macro_rules! select_bootloader {
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( $( $feature:literal => $loader:ident, )+ default => $default:ident ) => {
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$(
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#[cfg(feature = $feature)]
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#[link_section = ".boot2"]
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#[used]
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static BOOT2: [u8; 256] = rp2040_boot2::$loader;
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)*
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#[cfg(not(any( $( feature = $feature),* )))]
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#[link_section = ".boot2"]
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#[used]
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static BOOT2: [u8; 256] = rp2040_boot2::$default;
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}
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}
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#[cfg(all(not(feature = "boot2-none"), feature = "rp2040"))]
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select_bootloader! {
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"boot2-at25sf128a" => BOOT_LOADER_AT25SF128A,
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"boot2-gd25q64cs" => BOOT_LOADER_GD25Q64CS,
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"boot2-generic-03h" => BOOT_LOADER_GENERIC_03H,
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"boot2-is25lp080" => BOOT_LOADER_IS25LP080,
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"boot2-ram-memcpy" => BOOT_LOADER_RAM_MEMCPY,
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"boot2-w25q080" => BOOT_LOADER_W25Q080,
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"boot2-w25x10cl" => BOOT_LOADER_W25X10CL,
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default => BOOT_LOADER_W25Q080
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}
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#[cfg(all(not(feature = "imagedef-none"), feature = "_rp235x"))]
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macro_rules! select_imagedef {
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( $( $feature:literal => $imagedef:ident, )+ default => $default:ident ) => {
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$(
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#[cfg(feature = $feature)]
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#[link_section = ".start_block"]
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#[used]
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static IMAGE_DEF: crate::block::ImageDef = crate::block::ImageDef::$imagedef();
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)*
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#[cfg(not(any( $( feature = $feature),* )))]
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#[link_section = ".start_block"]
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#[used]
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static IMAGE_DEF: crate::block::ImageDef = crate::block::ImageDef::$default();
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}
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}
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#[cfg(all(not(feature = "imagedef-none"), feature = "_rp235x"))]
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select_imagedef! {
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"imagedef-secure-exe" => secure_exe,
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"imagedef-nonsecure-exe" => non_secure_exe,
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default => secure_exe
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}
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/// Installs a stack guard for the CORE0 stack in MPU region 0.
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/// Will fail if the MPU is already configured. This function requires
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/// a `_stack_end` symbol to be defined by the linker script, and expects
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/// `_stack_end` to be located at the lowest address (largest depth) of
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/// the stack.
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///
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/// This method can *only* set up stack guards on the currently
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/// executing core. Stack guards for CORE1 are set up automatically,
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/// only CORE0 should ever use this.
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///
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/// # Usage
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///
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/// ```no_run
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/// use embassy_rp::install_core0_stack_guard;
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/// use embassy_executor::{Executor, Spawner};
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///
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/// #[embassy_executor::main]
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/// async fn main(_spawner: Spawner) {
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/// // set up by the linker as follows:
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/// //
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/// // MEMORY {
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/// // STACK0: ORIGIN = 0x20040000, LENGTH = 4K
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/// // }
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/// //
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/// // _stack_end = ORIGIN(STACK0);
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/// // _stack_start = _stack_end + LENGTH(STACK0);
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/// //
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/// install_core0_stack_guard().expect("MPU already configured");
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/// let p = embassy_rp::init(Default::default());
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///
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/// // ...
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/// }
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/// ```
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pub fn install_core0_stack_guard() -> Result<(), ()> {
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extern "C" {
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static mut _stack_end: usize;
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}
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unsafe { install_stack_guard(core::ptr::addr_of_mut!(_stack_end)) }
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}
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#[cfg(all(feature = "rp2040", not(feature = "_test")))]
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#[inline(always)]
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unsafe fn install_stack_guard(stack_bottom: *mut usize) -> Result<(), ()> {
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let core = unsafe { cortex_m::Peripherals::steal() };
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// Fail if MPU is already configured
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if core.MPU.ctrl.read() != 0 {
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return Err(());
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}
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// The minimum we can protect is 32 bytes on a 32 byte boundary, so round up which will
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// just shorten the valid stack range a tad.
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let addr = (stack_bottom as u32 + 31) & !31;
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// Mask is 1 bit per 32 bytes of the 256 byte range... clear the bit for the segment we want
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let subregion_select = 0xff ^ (1 << ((addr >> 5) & 7));
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unsafe {
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core.MPU.ctrl.write(5); // enable mpu with background default map
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core.MPU.rbar.write((addr & !0xff) | (1 << 4)); // set address and update RNR
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core.MPU.rasr.write(
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1 // enable region
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| (0x7 << 1) // size 2^(7 + 1) = 256
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| (subregion_select << 8)
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| 0x10000000, // XN = disable instruction fetch; no other bits means no permissions
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|
);
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
#[cfg(all(feature = "_rp235x", not(feature = "_test")))]
|
|
#[inline(always)]
|
|
unsafe fn install_stack_guard(stack_bottom: *mut usize) -> Result<(), ()> {
|
|
let core = unsafe { cortex_m::Peripherals::steal() };
|
|
|
|
// Fail if MPU is already configured
|
|
if core.MPU.ctrl.read() != 0 {
|
|
return Err(());
|
|
}
|
|
|
|
unsafe {
|
|
core.MPU.ctrl.write(5); // enable mpu with background default map
|
|
core.MPU.rbar.write(stack_bottom as u32 & !0xff); // set address
|
|
core.MPU.rlar.write(1); // enable region
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
// This is to hack around cortex_m defaulting to ARMv7 when building tests,
|
|
// so the compile fails when we try to use ARMv8 peripherals.
|
|
#[cfg(feature = "_test")]
|
|
#[inline(always)]
|
|
unsafe fn install_stack_guard(_stack_bottom: *mut usize) -> Result<(), ()> {
|
|
Ok(())
|
|
}
|
|
|
|
/// HAL configuration for RP.
|
|
pub mod config {
|
|
use crate::clocks::ClockConfig;
|
|
|
|
/// HAL configuration passed when initializing.
|
|
#[non_exhaustive]
|
|
pub struct Config {
|
|
/// Clock configuration.
|
|
pub clocks: ClockConfig,
|
|
}
|
|
|
|
impl Default for Config {
|
|
fn default() -> Self {
|
|
Self {
|
|
clocks: ClockConfig::crystal(12_000_000),
|
|
}
|
|
}
|
|
}
|
|
|
|
impl Config {
|
|
/// Create a new configuration with the provided clock config.
|
|
pub fn new(clocks: ClockConfig) -> Self {
|
|
Self { clocks }
|
|
}
|
|
}
|
|
}
|
|
|
|
/// Initialize the `embassy-rp` HAL with the provided configuration.
|
|
///
|
|
/// This returns the peripheral singletons that can be used for creating drivers.
|
|
///
|
|
/// This should only be called once at startup, otherwise it panics.
|
|
pub fn init(config: config::Config) -> Peripherals {
|
|
// Do this first, so that it panics if user is calling `init` a second time
|
|
// before doing anything important.
|
|
let peripherals = Peripherals::take();
|
|
|
|
unsafe {
|
|
clocks::init(config.clocks);
|
|
#[cfg(feature = "time-driver")]
|
|
time_driver::init();
|
|
dma::init();
|
|
gpio::init();
|
|
}
|
|
|
|
peripherals
|
|
}
|
|
|
|
#[cfg(feature = "rt")]
|
|
#[cortex_m_rt::pre_init]
|
|
unsafe fn pre_init() {
|
|
// SIO does not get reset when core0 is reset with either `scb::sys_reset()` or with SWD.
|
|
// Since we're using SIO spinlock 31 for the critical-section impl, this causes random
|
|
// hangs if we reset in the middle of a CS, because the next boot sees the spinlock
|
|
// as locked and waits forever.
|
|
//
|
|
// See https://github.com/embassy-rs/embassy/issues/1736
|
|
// and https://github.com/rp-rs/rp-hal/issues/292
|
|
// and https://matrix.to/#/!vhKMWjizPZBgKeknOo:matrix.org/$VfOkQgyf1PjmaXZbtycFzrCje1RorAXd8BQFHTl4d5M
|
|
//
|
|
// According to Raspberry Pi, this is considered Working As Intended, and not an errata,
|
|
// even though this behavior is different from every other ARM chip (sys_reset usually resets
|
|
// the *system* as its name implies, not just the current core).
|
|
//
|
|
// To fix this, reset SIO on boot. We must do this in pre_init because it's unsound to do it
|
|
// in `embassy_rp::init`, since the user could've acquired a CS by then. pre_init is guaranteed
|
|
// to run before any user code.
|
|
//
|
|
// A similar thing could happen with PROC1. It is unclear whether it's possible for PROC1
|
|
// to stay unreset through a PROC0 reset, so we reset it anyway just in case.
|
|
//
|
|
// Important info from PSM logic (from Luke Wren in above Matrix thread)
|
|
//
|
|
// The logic is, each PSM stage is reset if either of the following is true:
|
|
// - The previous stage is in reset and FRCE_ON is false
|
|
// - FRCE_OFF is true
|
|
//
|
|
// The PSM order is SIO -> PROC0 -> PROC1.
|
|
// So, we have to force-on PROC0 to prevent it from getting reset when resetting SIO.
|
|
#[cfg(feature = "rp2040")]
|
|
{
|
|
pac::PSM.frce_on().write_and_wait(|w| {
|
|
w.set_proc0(true);
|
|
});
|
|
// Then reset SIO and PROC1.
|
|
pac::PSM.frce_off().write_and_wait(|w| {
|
|
w.set_sio(true);
|
|
w.set_proc1(true);
|
|
});
|
|
// clear force_off first, force_on second. The other way around would reset PROC0.
|
|
pac::PSM.frce_off().write_and_wait(|_| {});
|
|
pac::PSM.frce_on().write_and_wait(|_| {});
|
|
}
|
|
|
|
#[cfg(feature = "_rp235x")]
|
|
{
|
|
// on RP235x, datasheet says "The FRCE_ON register is a development feature that does nothing in production devices."
|
|
// No idea why they removed it. Removing it means we can't use PSM to reset SIO, because it comes before
|
|
// PROC0, so we'd need FRCE_ON to prevent resetting ourselves.
|
|
//
|
|
// So we just unlock the spinlock manually.
|
|
pac::SIO.spinlock(31).write_value(1);
|
|
|
|
// We can still use PSM to reset PROC1 since it comes after PROC0 in the state machine.
|
|
pac::PSM.frce_off().write_and_wait(|w| w.set_proc1(true));
|
|
pac::PSM.frce_off().write_and_wait(|_| {});
|
|
|
|
// Make atomics work between cores.
|
|
enable_actlr_extexclall();
|
|
}
|
|
}
|
|
|
|
/// Set the EXTEXCLALL bit in ACTLR.
|
|
///
|
|
/// The default MPU memory map marks all memory as non-shareable, so atomics don't
|
|
/// synchronize memory accesses between cores at all. This bit forces all memory to be
|
|
/// considered shareable regardless of what the MPU says.
|
|
///
|
|
/// TODO: does this interfere somehow if the user wants to use a custom MPU configuration?
|
|
/// maybe we need to add a way to disable this?
|
|
///
|
|
/// This must be done FOR EACH CORE.
|
|
#[cfg(feature = "_rp235x")]
|
|
unsafe fn enable_actlr_extexclall() {
|
|
(&*cortex_m::peripheral::ICB::PTR).actlr.modify(|w| w | (1 << 29));
|
|
}
|
|
|
|
/// Extension trait for PAC regs, adding atomic xor/bitset/bitclear writes.
|
|
#[allow(unused)]
|
|
trait RegExt<T: Copy> {
|
|
#[allow(unused)]
|
|
fn write_xor<R>(&self, f: impl FnOnce(&mut T) -> R) -> R;
|
|
fn write_set<R>(&self, f: impl FnOnce(&mut T) -> R) -> R;
|
|
fn write_clear<R>(&self, f: impl FnOnce(&mut T) -> R) -> R;
|
|
fn write_and_wait<R>(&self, f: impl FnOnce(&mut T) -> R) -> R
|
|
where
|
|
T: PartialEq;
|
|
}
|
|
|
|
impl<T: Default + Copy, A: pac::common::Write> RegExt<T> for pac::common::Reg<T, A> {
|
|
fn write_xor<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
|
|
let mut val = Default::default();
|
|
let res = f(&mut val);
|
|
unsafe {
|
|
let ptr = (self.as_ptr() as *mut u8).add(0x1000) as *mut T;
|
|
ptr.write_volatile(val);
|
|
}
|
|
res
|
|
}
|
|
|
|
fn write_set<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
|
|
let mut val = Default::default();
|
|
let res = f(&mut val);
|
|
unsafe {
|
|
let ptr = (self.as_ptr() as *mut u8).add(0x2000) as *mut T;
|
|
ptr.write_volatile(val);
|
|
}
|
|
res
|
|
}
|
|
|
|
fn write_clear<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
|
|
let mut val = Default::default();
|
|
let res = f(&mut val);
|
|
unsafe {
|
|
let ptr = (self.as_ptr() as *mut u8).add(0x3000) as *mut T;
|
|
ptr.write_volatile(val);
|
|
}
|
|
res
|
|
}
|
|
|
|
fn write_and_wait<R>(&self, f: impl FnOnce(&mut T) -> R) -> R
|
|
where
|
|
T: PartialEq,
|
|
{
|
|
let mut val = Default::default();
|
|
let res = f(&mut val);
|
|
unsafe {
|
|
self.as_ptr().write_volatile(val);
|
|
while self.as_ptr().read_volatile() != val {}
|
|
}
|
|
res
|
|
}
|
|
}
|