146 lines
3.8 KiB
Rust
146 lines
3.8 KiB
Rust
//! Flash memory (FLASH)
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use embedded_storage::nor_flash::{NorFlashError, NorFlashErrorKind};
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#[cfg(flash_f4)]
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mod asynch;
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#[cfg(flash)]
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mod common;
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#[cfg(eeprom)]
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mod eeprom;
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#[cfg(flash_f4)]
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pub use asynch::InterruptHandler;
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#[cfg(flash)]
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pub use common::*;
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#[cfg(eeprom)]
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#[allow(unused_imports)]
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pub use eeprom::*;
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pub use crate::_generated::flash_regions::*;
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#[cfg(eeprom)]
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pub use crate::_generated::{EEPROM_BASE, EEPROM_SIZE};
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pub use crate::_generated::{FLASH_BASE, FLASH_SIZE, MAX_ERASE_SIZE, WRITE_SIZE};
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/// Get all flash regions.
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pub fn get_flash_regions() -> &'static [&'static FlashRegion] {
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&FLASH_REGIONS
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}
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/// Read size (always 1)
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pub const READ_SIZE: usize = 1;
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/// Blocking flash mode typestate.
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pub enum Blocking {}
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/// Async flash mode typestate.
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pub enum Async {}
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/// Flash memory region
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub struct FlashRegion {
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/// Bank number.
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pub bank: FlashBank,
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/// Absolute base address.
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pub base: u32,
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/// Size in bytes.
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pub size: u32,
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/// Erase size (sector size).
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pub erase_size: u32,
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/// Minimum write size.
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pub write_size: u32,
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/// Erase value (usually `0xFF`, but is `0x00` in some chips)
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pub erase_value: u8,
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pub(crate) _ensure_internal: (),
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}
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impl FlashRegion {
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/// Absolute end address.
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pub const fn end(&self) -> u32 {
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self.base + self.size
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}
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/// Number of sectors in the region.
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pub const fn sectors(&self) -> u8 {
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(self.size / self.erase_size) as u8
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}
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}
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/// Flash sector.
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#[derive(Debug, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub struct FlashSector {
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/// Bank number.
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pub bank: FlashBank,
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/// Sector number within the bank.
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pub index_in_bank: u8,
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/// Absolute start address.
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pub start: u32,
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/// Size in bytes.
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pub size: u32,
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}
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/// Flash bank.
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#[derive(Clone, Copy, Debug, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum FlashBank {
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/// Bank 1
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Bank1 = 0,
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/// Bank 2
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Bank2 = 1,
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/// OTP region,
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Otp,
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}
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#[cfg(all(eeprom, not(any(flash_l0, flash_l1))))]
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compile_error!("The 'eeprom' cfg is enabled for a non-L0/L1 chip family. This is an unsupported configuration.");
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#[cfg_attr(any(flash_l0, flash_l1, flash_l4, flash_l5, flash_wl, flash_wb), path = "l.rs")]
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#[cfg_attr(flash_f0, path = "f0.rs")]
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#[cfg_attr(any(flash_f1, flash_f3), path = "f1f3.rs")]
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#[cfg_attr(flash_f2, path = "f2.rs")]
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#[cfg_attr(flash_f4, path = "f4.rs")]
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#[cfg_attr(flash_f7, path = "f7.rs")]
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#[cfg_attr(any(flash_g0x0, flash_g0x1, flash_g4c2, flash_g4c3, flash_g4c4), path = "g.rs")]
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#[cfg_attr(flash_h7, path = "h7.rs")]
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#[cfg_attr(flash_h7ab, path = "h7.rs")]
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#[cfg_attr(flash_u5, path = "u5.rs")]
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#[cfg_attr(flash_h5, path = "h5.rs")]
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#[cfg_attr(flash_h50, path = "h50.rs")]
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#[cfg_attr(flash_u0, path = "u0.rs")]
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#[cfg_attr(
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not(any(
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flash_l0, flash_l1, flash_l4, flash_l5, flash_wl, flash_wb, flash_f0, flash_f1, flash_f2, flash_f3, flash_f4,
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flash_f7, flash_g0x0, flash_g0x1, flash_g4c2, flash_g4c3, flash_g4c4, flash_h7, flash_h7ab, flash_u5,
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flash_h50, flash_u0, flash_h5,
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)),
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path = "other.rs"
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)]
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mod family;
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#[allow(unused_imports)]
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pub use family::*;
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/// Flash error
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///
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/// See STM32 Reference Manual for your chip for details.
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#[allow(missing_docs)]
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Error {
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Prog,
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Size,
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Miss,
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Seq,
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Protected,
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Unaligned,
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Parallelism,
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}
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impl NorFlashError for Error {
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fn kind(&self) -> NorFlashErrorKind {
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match self {
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Self::Size => NorFlashErrorKind::OutOfBounds,
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Self::Unaligned => NorFlashErrorKind::NotAligned,
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_ => NorFlashErrorKind::Other,
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}
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}
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}
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