336 lines
11 KiB
Rust
336 lines
11 KiB
Rust
// The v1c ethernet driver was ported to embassy from the awesome stm32-eth project (https://github.com/stm32-rs/stm32-eth).
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mod rx_desc;
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mod tx_desc;
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use core::sync::atomic::{fence, Ordering};
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use embassy_cortex_m::interrupt::InterruptExt;
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use embassy_hal_common::{into_ref, PeripheralRef};
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use stm32_metapac::eth::vals::{Apcs, Cr, Dm, DmaomrSr, Fes, Ftf, Ifg, MbProgress, Mw, Pbl, Rsf, St, Tsf};
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pub(crate) use self::rx_desc::{RDes, RDesRing};
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pub(crate) use self::tx_desc::{TDes, TDesRing};
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use super::*;
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use crate::gpio::sealed::{AFType, Pin as __GpioPin};
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use crate::gpio::AnyPin;
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#[cfg(eth_v1a)]
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use crate::pac::AFIO;
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#[cfg(any(eth_v1b, eth_v1c))]
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use crate::pac::SYSCFG;
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use crate::pac::{ETH, RCC};
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use crate::Peripheral;
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pub struct Ethernet<'d, T: Instance, P: PHY> {
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_peri: PeripheralRef<'d, T>,
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pub(crate) tx: TDesRing<'d>,
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pub(crate) rx: RDesRing<'d>,
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pins: [PeripheralRef<'d, AnyPin>; 9],
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_phy: P,
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clock_range: Cr,
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phy_addr: u8,
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pub(crate) mac_addr: [u8; 6],
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}
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#[cfg(eth_v1a)]
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macro_rules! config_in_pins {
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($($pin:ident),*) => {
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// NOTE(unsafe) Exclusive access to the registers
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critical_section::with(|_| {
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$(
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// TODO properly create a set_as_input function
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$pin.set_as_af($pin.af_num(), AFType::Input);
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)*
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})
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}
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}
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#[cfg(eth_v1a)]
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macro_rules! config_af_pins {
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($($pin:ident),*) => {
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// NOTE(unsafe) Exclusive access to the registers
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critical_section::with(|_| {
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$(
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// We are lucky here, this configures to max speed (50MHz)
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$pin.set_as_af($pin.af_num(), AFType::OutputPushPull);
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)*
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})
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};
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}
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#[cfg(any(eth_v1b, eth_v1c))]
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macro_rules! config_pins {
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($($pin:ident),*) => {
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// NOTE(unsafe) Exclusive access to the registers
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critical_section::with(|_| {
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$(
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$pin.set_as_af($pin.af_num(), AFType::OutputPushPull);
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$pin.set_speed(crate::gpio::Speed::VeryHigh);
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)*
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})
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};
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}
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impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
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/// safety: the returned instance is not leak-safe
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pub fn new<const TX: usize, const RX: usize>(
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queue: &'d mut PacketQueue<TX, RX>,
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peri: impl Peripheral<P = T> + 'd,
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interrupt: impl Peripheral<P = crate::interrupt::ETH> + 'd,
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ref_clk: impl Peripheral<P = impl RefClkPin<T>> + 'd,
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mdio: impl Peripheral<P = impl MDIOPin<T>> + 'd,
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mdc: impl Peripheral<P = impl MDCPin<T>> + 'd,
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crs: impl Peripheral<P = impl CRSPin<T>> + 'd,
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rx_d0: impl Peripheral<P = impl RXD0Pin<T>> + 'd,
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rx_d1: impl Peripheral<P = impl RXD1Pin<T>> + 'd,
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tx_d0: impl Peripheral<P = impl TXD0Pin<T>> + 'd,
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tx_d1: impl Peripheral<P = impl TXD1Pin<T>> + 'd,
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tx_en: impl Peripheral<P = impl TXEnPin<T>> + 'd,
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phy: P,
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mac_addr: [u8; 6],
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phy_addr: u8,
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) -> Self {
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into_ref!(peri, interrupt, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
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unsafe {
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// Enable the necessary Clocks
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// NOTE(unsafe) We have exclusive access to the registers
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#[cfg(eth_v1a)]
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critical_section::with(|_| {
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RCC.apb2enr().modify(|w| w.set_afioen(true));
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// Select RMII (Reduced Media Independent Interface)
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// Must be done prior to enabling peripheral clock
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AFIO.mapr().modify(|w| w.set_mii_rmii_sel(true));
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RCC.ahbenr().modify(|w| {
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w.set_ethen(true);
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w.set_ethtxen(true);
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w.set_ethrxen(true);
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});
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});
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#[cfg(any(eth_v1b, eth_v1c))]
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critical_section::with(|_| {
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RCC.apb2enr().modify(|w| w.set_syscfgen(true));
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RCC.ahb1enr().modify(|w| {
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w.set_ethen(true);
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w.set_ethtxen(true);
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w.set_ethrxen(true);
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});
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// RMII (Reduced Media Independent Interface)
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SYSCFG.pmc().modify(|w| w.set_mii_rmii_sel(true));
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});
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#[cfg(eth_v1a)]
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{
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config_in_pins!(ref_clk, rx_d0, rx_d1);
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config_af_pins!(mdio, mdc, tx_d0, tx_d1, tx_en);
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}
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#[cfg(any(eth_v1b, eth_v1c))]
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config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
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// NOTE(unsafe) We have exclusive access to the registers
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let dma = ETH.ethernet_dma();
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let mac = ETH.ethernet_mac();
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// Reset and wait
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dma.dmabmr().modify(|w| w.set_sr(true));
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while dma.dmabmr().read().sr() {}
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mac.maccr().modify(|w| {
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w.set_ifg(Ifg::IFG96); // inter frame gap 96 bit times
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w.set_apcs(Apcs::STRIP); // automatic padding and crc stripping
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w.set_fes(Fes::FES100); // fast ethernet speed
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w.set_dm(Dm::FULLDUPLEX); // full duplex
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// TODO: Carrier sense ? ECRSFD
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});
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// Note: Writing to LR triggers synchronisation of both LR and HR into the MAC core,
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// so the LR write must happen after the HR write.
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mac.maca0hr()
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.modify(|w| w.set_maca0h(u16::from(mac_addr[4]) | (u16::from(mac_addr[5]) << 8)));
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mac.maca0lr().write(|w| {
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w.set_maca0l(
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u32::from(mac_addr[0])
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| (u32::from(mac_addr[1]) << 8)
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| (u32::from(mac_addr[2]) << 16)
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| (u32::from(mac_addr[3]) << 24),
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)
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});
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// pause time
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mac.macfcr().modify(|w| w.set_pt(0x100));
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// Transfer and Forward, Receive and Forward
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dma.dmaomr().modify(|w| {
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w.set_tsf(Tsf::STOREFORWARD);
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w.set_rsf(Rsf::STOREFORWARD);
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});
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dma.dmabmr().modify(|w| {
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w.set_pbl(Pbl::PBL32) // programmable burst length - 32 ?
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});
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// TODO MTU size setting not found for v1 ethernet, check if correct
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// NOTE(unsafe) We got the peripheral singleton, which means that `rcc::init` was called
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let hclk = crate::rcc::get_freqs().ahb1;
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let hclk_mhz = hclk.0 / 1_000_000;
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// Set the MDC clock frequency in the range 1MHz - 2.5MHz
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let clock_range = match hclk_mhz {
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0..=24 => panic!("Invalid HCLK frequency - should be at least 25 MHz."),
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25..=34 => Cr::CR_20_35, // Divide by 16
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35..=59 => Cr::CR_35_60, // Divide by 26
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60..=99 => Cr::CR_60_100, // Divide by 42
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100..=149 => Cr::CR_100_150, // Divide by 62
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150..=216 => Cr::CR_150_168, // Divide by 102
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_ => {
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panic!("HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider")
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}
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};
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let pins = [
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ref_clk.map_into(),
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mdio.map_into(),
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mdc.map_into(),
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crs.map_into(),
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rx_d0.map_into(),
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rx_d1.map_into(),
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tx_d0.map_into(),
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tx_d1.map_into(),
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tx_en.map_into(),
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];
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let mut this = Self {
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_peri: peri,
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pins,
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_phy: phy,
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clock_range,
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phy_addr,
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mac_addr,
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tx: TDesRing::new(&mut queue.tx_desc, &mut queue.tx_buf),
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rx: RDesRing::new(&mut queue.rx_desc, &mut queue.rx_buf),
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};
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fence(Ordering::SeqCst);
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let mac = ETH.ethernet_mac();
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let dma = ETH.ethernet_dma();
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mac.maccr().modify(|w| {
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w.set_re(true);
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w.set_te(true);
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});
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dma.dmaomr().modify(|w| {
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w.set_ftf(Ftf::FLUSH); // flush transmit fifo (queue)
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w.set_st(St::STARTED); // start transmitting channel
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w.set_sr(DmaomrSr::STARTED); // start receiving channel
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});
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this.rx.demand_poll();
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// Enable interrupts
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dma.dmaier().modify(|w| {
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w.set_nise(true);
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w.set_rie(true);
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w.set_tie(true);
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});
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P::phy_reset(&mut this);
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P::phy_init(&mut this);
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interrupt.set_handler(Self::on_interrupt);
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interrupt.enable();
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this
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}
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}
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fn on_interrupt(_cx: *mut ()) {
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WAKER.wake();
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// TODO: Check and clear more flags
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unsafe {
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let dma = ETH.ethernet_dma();
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dma.dmasr().modify(|w| {
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w.set_ts(true);
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w.set_rs(true);
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w.set_nis(true);
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});
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// Delay two peripheral's clock
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dma.dmasr().read();
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dma.dmasr().read();
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}
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}
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}
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unsafe impl<'d, T: Instance, P: PHY> StationManagement for Ethernet<'d, T, P> {
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fn smi_read(&mut self, reg: u8) -> u16 {
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// NOTE(unsafe) These registers aren't used in the interrupt and we have `&mut self`
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unsafe {
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let mac = ETH.ethernet_mac();
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mac.macmiiar().modify(|w| {
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w.set_pa(self.phy_addr);
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w.set_mr(reg);
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w.set_mw(Mw::READ); // read operation
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w.set_cr(self.clock_range);
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w.set_mb(MbProgress::BUSY); // indicate that operation is in progress
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});
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while mac.macmiiar().read().mb() == MbProgress::BUSY {}
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mac.macmiidr().read().md()
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}
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}
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fn smi_write(&mut self, reg: u8, val: u16) {
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// NOTE(unsafe) These registers aren't used in the interrupt and we have `&mut self`
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unsafe {
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let mac = ETH.ethernet_mac();
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mac.macmiidr().write(|w| w.set_md(val));
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mac.macmiiar().modify(|w| {
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w.set_pa(self.phy_addr);
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w.set_mr(reg);
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w.set_mw(Mw::WRITE); // write
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w.set_cr(self.clock_range);
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w.set_mb(MbProgress::BUSY);
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});
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while mac.macmiiar().read().mb() == MbProgress::BUSY {}
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}
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}
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}
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impl<'d, T: Instance, P: PHY> Drop for Ethernet<'d, T, P> {
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fn drop(&mut self) {
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// NOTE(unsafe) We have `&mut self` and the interrupt doesn't use this registers
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unsafe {
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let dma = ETH.ethernet_dma();
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let mac = ETH.ethernet_mac();
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// Disable the TX DMA and wait for any previous transmissions to be completed
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dma.dmaomr().modify(|w| w.set_st(St::STOPPED));
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// Disable MAC transmitter and receiver
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mac.maccr().modify(|w| {
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w.set_re(false);
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w.set_te(false);
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});
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dma.dmaomr().modify(|w| w.set_sr(DmaomrSr::STOPPED));
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}
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// NOTE(unsafe) Exclusive access to the regs
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critical_section::with(|_| unsafe {
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for pin in self.pins.iter_mut() {
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pin.set_as_disconnected();
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}
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})
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}
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}
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