947 lines
29 KiB
Rust
947 lines
29 KiB
Rust
use core::cmp;
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use core::marker::PhantomData;
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use core::task::Poll;
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use atomic_polyfill::{AtomicUsize, Ordering};
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use embassy::waitqueue::AtomicWaker;
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use embassy_hal_common::drop::OnDrop;
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use embassy_hal_common::unborrow;
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use futures::future::poll_fn;
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use crate::dma::NoDma;
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use crate::gpio::sealed::AFType;
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use crate::i2c::{Error, Instance, SclPin, SdaPin};
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use crate::interrupt::InterruptExt;
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use crate::pac::i2c;
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use crate::time::Hertz;
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use crate::Unborrow;
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pub struct State {
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waker: AtomicWaker,
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chunks_transferred: AtomicUsize,
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}
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impl State {
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pub(crate) const fn new() -> Self {
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Self {
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waker: AtomicWaker::new(),
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chunks_transferred: AtomicUsize::new(0),
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}
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}
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}
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pub struct I2c<'d, T: Instance, TXDMA = NoDma, RXDMA = NoDma> {
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phantom: PhantomData<&'d mut T>,
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tx_dma: TXDMA,
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#[allow(dead_code)]
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rx_dma: RXDMA,
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}
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impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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pub fn new<F>(
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_peri: impl Unborrow<Target = T> + 'd,
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scl: impl Unborrow<Target = impl SclPin<T>> + 'd,
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sda: impl Unborrow<Target = impl SdaPin<T>> + 'd,
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irq: impl Unborrow<Target = T::Interrupt> + 'd,
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tx_dma: impl Unborrow<Target = TXDMA> + 'd,
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rx_dma: impl Unborrow<Target = RXDMA> + 'd,
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freq: F,
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) -> Self
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where
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F: Into<Hertz>,
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{
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unborrow!(irq, scl, sda, tx_dma, rx_dma);
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T::enable();
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T::reset();
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unsafe {
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scl.set_as_af(scl.af_num(), AFType::OutputOpenDrain);
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sda.set_as_af(sda.af_num(), AFType::OutputOpenDrain);
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}
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unsafe {
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T::regs().cr1().modify(|reg| {
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reg.set_pe(false);
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reg.set_anfoff(false);
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});
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}
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let timings = Timings::new(T::frequency(), freq.into());
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unsafe {
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T::regs().timingr().write(|reg| {
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reg.set_presc(timings.prescale);
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reg.set_scll(timings.scll);
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reg.set_sclh(timings.sclh);
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reg.set_sdadel(timings.sdadel);
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reg.set_scldel(timings.scldel);
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});
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}
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unsafe {
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T::regs().cr1().modify(|reg| {
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reg.set_pe(true);
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});
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}
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irq.set_handler(Self::on_interrupt);
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irq.unpend();
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irq.enable();
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Self {
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phantom: PhantomData,
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tx_dma,
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rx_dma,
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}
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}
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unsafe fn on_interrupt(_: *mut ()) {
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let regs = T::regs();
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let isr = regs.isr().read();
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if isr.tcr() || isr.tc() {
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let state = T::state();
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state.chunks_transferred.fetch_add(1, Ordering::Relaxed);
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state.waker.wake();
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}
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// The flag can only be cleared by writting to nbytes, we won't do that here, so disable
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// the interrupt
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critical_section::with(|_| {
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regs.cr1().modify(|w| w.set_tcie(false));
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});
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}
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fn master_stop(&mut self) {
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unsafe {
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T::regs().cr2().write(|w| w.set_stop(true));
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}
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}
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unsafe fn master_read(address: u8, length: usize, stop: Stop, reload: bool, restart: bool) {
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assert!(length < 256);
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if !restart {
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// Wait for any previous address sequence to end
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// automatically. This could be up to 50% of a bus
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// cycle (ie. up to 0.5/freq)
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while T::regs().cr2().read().start() {}
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}
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// Set START and prepare to receive bytes into
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// `buffer`. The START bit can be set even if the bus
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// is BUSY or I2C is in slave mode.
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let reload = if reload {
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i2c::vals::Reload::NOTCOMPLETED
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} else {
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i2c::vals::Reload::COMPLETED
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};
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T::regs().cr2().modify(|w| {
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w.set_sadd((address << 1 | 0) as u16);
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w.set_add10(i2c::vals::Addmode::BIT7);
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w.set_dir(i2c::vals::Dir::READ);
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w.set_nbytes(length as u8);
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w.set_start(true);
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w.set_autoend(stop.autoend());
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w.set_reload(reload);
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});
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}
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unsafe fn master_write(address: u8, length: usize, stop: Stop, reload: bool) {
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assert!(length < 256);
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// Wait for any previous address sequence to end
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// automatically. This could be up to 50% of a bus
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// cycle (ie. up to 0.5/freq)
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while T::regs().cr2().read().start() {}
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let reload = if reload {
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i2c::vals::Reload::NOTCOMPLETED
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} else {
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i2c::vals::Reload::COMPLETED
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};
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// Set START and prepare to send `bytes`. The
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// START bit can be set even if the bus is BUSY or
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// I2C is in slave mode.
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T::regs().cr2().modify(|w| {
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w.set_sadd((address << 1 | 0) as u16);
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w.set_add10(i2c::vals::Addmode::BIT7);
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w.set_dir(i2c::vals::Dir::WRITE);
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w.set_nbytes(length as u8);
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w.set_start(true);
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w.set_autoend(stop.autoend());
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w.set_reload(reload);
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});
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}
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unsafe fn master_continue(length: usize, reload: bool) {
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assert!(length < 256 && length > 0);
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while !T::regs().isr().read().tcr() {}
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let reload = if reload {
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i2c::vals::Reload::NOTCOMPLETED
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} else {
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i2c::vals::Reload::COMPLETED
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};
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T::regs().cr2().modify(|w| {
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w.set_nbytes(length as u8);
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w.set_reload(reload);
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});
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}
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fn flush_txdr(&self) {
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//if $i2c.isr.read().txis().bit_is_set() {
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//$i2c.txdr.write(|w| w.txdata().bits(0));
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//}
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unsafe {
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if T::regs().isr().read().txis() {
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T::regs().txdr().write(|w| w.set_txdata(0));
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}
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if T::regs().isr().read().txe() {
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T::regs().isr().modify(|w| w.set_txe(true))
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}
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}
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// If TXDR is not flagged as empty, write 1 to flush it
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//if $i2c.isr.read().txe().is_not_empty() {
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//$i2c.isr.write(|w| w.txe().set_bit());
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//}
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}
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fn wait_txe(&self) -> Result<(), Error> {
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loop {
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unsafe {
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let isr = T::regs().isr().read();
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if isr.txe() {
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return Ok(());
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} else if isr.berr() {
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T::regs().icr().write(|reg| reg.set_berrcf(true));
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return Err(Error::Bus);
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} else if isr.arlo() {
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T::regs().icr().write(|reg| reg.set_arlocf(true));
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return Err(Error::Arbitration);
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} else if isr.nackf() {
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T::regs().icr().write(|reg| reg.set_nackcf(true));
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self.flush_txdr();
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return Err(Error::Nack);
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}
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}
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}
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}
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fn wait_rxne(&self) -> Result<(), Error> {
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loop {
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unsafe {
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let isr = T::regs().isr().read();
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if isr.rxne() {
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return Ok(());
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} else if isr.berr() {
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T::regs().icr().write(|reg| reg.set_berrcf(true));
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return Err(Error::Bus);
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} else if isr.arlo() {
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T::regs().icr().write(|reg| reg.set_arlocf(true));
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return Err(Error::Arbitration);
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} else if isr.nackf() {
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T::regs().icr().write(|reg| reg.set_nackcf(true));
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self.flush_txdr();
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return Err(Error::Nack);
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}
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}
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}
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}
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fn wait_tc(&self) -> Result<(), Error> {
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loop {
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unsafe {
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let isr = T::regs().isr().read();
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if isr.tc() {
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return Ok(());
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} else if isr.berr() {
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T::regs().icr().write(|reg| reg.set_berrcf(true));
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return Err(Error::Bus);
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} else if isr.arlo() {
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T::regs().icr().write(|reg| reg.set_arlocf(true));
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return Err(Error::Arbitration);
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} else if isr.nackf() {
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T::regs().icr().write(|reg| reg.set_nackcf(true));
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self.flush_txdr();
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return Err(Error::Nack);
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}
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}
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}
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}
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fn read_internal(&mut self, address: u8, buffer: &mut [u8], restart: bool) -> Result<(), Error> {
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let completed_chunks = buffer.len() / 255;
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let total_chunks = if completed_chunks * 255 == buffer.len() {
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completed_chunks
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} else {
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completed_chunks + 1
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};
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let last_chunk_idx = total_chunks.saturating_sub(1);
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unsafe {
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Self::master_read(
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address,
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buffer.len().min(255),
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Stop::Automatic,
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last_chunk_idx != 0,
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restart,
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);
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}
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for (number, chunk) in buffer.chunks_mut(255).enumerate() {
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if number != 0 {
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// NOTE(unsafe) We have &mut self
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unsafe {
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Self::master_continue(chunk.len(), number != last_chunk_idx);
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}
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}
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for byte in chunk {
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// Wait until we have received something
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self.wait_rxne()?;
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unsafe {
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*byte = T::regs().rxdr().read().rxdata();
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}
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}
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}
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Ok(())
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}
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fn write_internal(&mut self, address: u8, bytes: &[u8], send_stop: bool) -> Result<(), Error> {
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let completed_chunks = bytes.len() / 255;
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let total_chunks = if completed_chunks * 255 == bytes.len() {
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completed_chunks
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} else {
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completed_chunks + 1
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};
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let last_chunk_idx = total_chunks.saturating_sub(1);
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// I2C start
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//
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// ST SAD+W
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// NOTE(unsafe) We have &mut self
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unsafe {
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Self::master_write(address, bytes.len().min(255), Stop::Software, last_chunk_idx != 0);
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}
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for (number, chunk) in bytes.chunks(255).enumerate() {
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if number != 0 {
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// NOTE(unsafe) We have &mut self
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unsafe {
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Self::master_continue(chunk.len(), number != last_chunk_idx);
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}
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}
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for byte in chunk {
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// Wait until we are allowed to send data
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// (START has been ACKed or last byte when
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// through)
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self.wait_txe()?;
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unsafe {
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T::regs().txdr().write(|w| w.set_txdata(*byte));
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}
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}
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}
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// Wait until the write finishes
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self.wait_tc()?;
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if send_stop {
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self.master_stop();
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}
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Ok(())
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}
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async fn write_dma_internal(
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&mut self,
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address: u8,
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bytes: &[u8],
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first_slice: bool,
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last_slice: bool,
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) -> Result<(), Error>
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where
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TXDMA: crate::i2c::TxDma<T>,
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{
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let total_len = bytes.len();
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let completed_chunks = total_len / 255;
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let total_chunks = if completed_chunks * 255 == total_len {
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completed_chunks
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} else {
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completed_chunks + 1
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};
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let dma_transfer = unsafe {
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let regs = T::regs();
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regs.cr1().modify(|w| {
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w.set_txdmaen(true);
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if first_slice {
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w.set_tcie(true);
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}
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});
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let dst = regs.txdr().ptr() as *mut u8;
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let ch = &mut self.tx_dma;
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let request = ch.request();
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crate::dma::write(ch, request, bytes, dst)
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};
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let state = T::state();
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state.chunks_transferred.store(0, Ordering::Relaxed);
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let mut remaining_len = total_len;
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let _on_drop = OnDrop::new(|| {
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let regs = T::regs();
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unsafe {
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regs.cr1().modify(|w| {
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if last_slice {
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w.set_txdmaen(false);
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}
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w.set_tcie(false);
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})
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}
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});
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// NOTE(unsafe) self.tx_dma does not fiddle with the i2c registers
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if first_slice {
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unsafe {
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Self::master_write(
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address,
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total_len.min(255),
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Stop::Software,
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(total_chunks != 1) || !last_slice,
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);
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}
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} else {
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unsafe {
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Self::master_continue(total_len.min(255), (total_chunks != 1) || !last_slice);
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T::regs().cr1().modify(|w| w.set_tcie(true));
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}
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}
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poll_fn(|cx| {
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state.waker.register(cx.waker());
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let chunks_transferred = state.chunks_transferred.load(Ordering::Relaxed);
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if chunks_transferred == total_chunks {
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return Poll::Ready(());
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} else if chunks_transferred != 0 {
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remaining_len = remaining_len.saturating_sub(255);
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let last_piece = (chunks_transferred + 1 == total_chunks) && last_slice;
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// NOTE(unsafe) self.tx_dma does not fiddle with the i2c registers
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unsafe {
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Self::master_continue(remaining_len.min(255), !last_piece);
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T::regs().cr1().modify(|w| w.set_tcie(true));
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}
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}
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Poll::Pending
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})
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.await;
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dma_transfer.await;
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if last_slice {
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// This should be done already
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self.wait_tc()?;
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self.master_stop();
|
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}
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Ok(())
|
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}
|
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|
|
async fn read_dma_internal(&mut self, address: u8, buffer: &mut [u8], restart: bool) -> Result<(), Error>
|
|
where
|
|
RXDMA: crate::i2c::RxDma<T>,
|
|
{
|
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let total_len = buffer.len();
|
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let completed_chunks = total_len / 255;
|
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let total_chunks = if completed_chunks * 255 == total_len {
|
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completed_chunks
|
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} else {
|
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completed_chunks + 1
|
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};
|
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|
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let dma_transfer = unsafe {
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let regs = T::regs();
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regs.cr1().modify(|w| {
|
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w.set_rxdmaen(true);
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w.set_tcie(true);
|
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});
|
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let src = regs.rxdr().ptr() as *mut u8;
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|
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let ch = &mut self.rx_dma;
|
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let request = ch.request();
|
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crate::dma::read(ch, request, src, buffer)
|
|
};
|
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|
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let state = T::state();
|
|
state.chunks_transferred.store(0, Ordering::Relaxed);
|
|
let mut remaining_len = total_len;
|
|
|
|
let _on_drop = OnDrop::new(|| {
|
|
let regs = T::regs();
|
|
unsafe {
|
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regs.cr1().modify(|w| {
|
|
w.set_rxdmaen(false);
|
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w.set_tcie(false);
|
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})
|
|
}
|
|
});
|
|
|
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// NOTE(unsafe) self.rx_dma does not fiddle with the i2c registers
|
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unsafe {
|
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Self::master_read(address, total_len.min(255), Stop::Software, total_chunks != 1, restart);
|
|
}
|
|
|
|
poll_fn(|cx| {
|
|
state.waker.register(cx.waker());
|
|
let chunks_transferred = state.chunks_transferred.load(Ordering::Relaxed);
|
|
|
|
if chunks_transferred == total_chunks {
|
|
return Poll::Ready(());
|
|
} else if chunks_transferred != 0 {
|
|
remaining_len = remaining_len.saturating_sub(255);
|
|
let last_piece = chunks_transferred + 1 == total_chunks;
|
|
|
|
// NOTE(unsafe) self.rx_dma does not fiddle with the i2c registers
|
|
unsafe {
|
|
Self::master_continue(remaining_len.min(255), !last_piece);
|
|
T::regs().cr1().modify(|w| w.set_tcie(true));
|
|
}
|
|
}
|
|
Poll::Pending
|
|
})
|
|
.await;
|
|
|
|
dma_transfer.await;
|
|
|
|
// This should be done already
|
|
self.wait_tc()?;
|
|
self.master_stop();
|
|
Ok(())
|
|
}
|
|
|
|
// =========================
|
|
// Async public API
|
|
|
|
pub async fn write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Error>
|
|
where
|
|
TXDMA: crate::i2c::TxDma<T>,
|
|
{
|
|
if bytes.is_empty() {
|
|
self.write_internal(address, bytes, true)
|
|
} else {
|
|
self.write_dma_internal(address, bytes, true, true).await
|
|
}
|
|
}
|
|
|
|
pub async fn write_vectored(&mut self, address: u8, bytes: &[&[u8]]) -> Result<(), Error>
|
|
where
|
|
TXDMA: crate::i2c::TxDma<T>,
|
|
{
|
|
if bytes.is_empty() {
|
|
return Err(Error::ZeroLengthTransfer);
|
|
}
|
|
let mut iter = bytes.iter();
|
|
|
|
let mut first = true;
|
|
let mut current = iter.next();
|
|
while let Some(c) = current {
|
|
let next = iter.next();
|
|
let is_last = next.is_none();
|
|
|
|
self.write_dma_internal(address, c, first, is_last).await?;
|
|
first = false;
|
|
current = next;
|
|
}
|
|
Ok(())
|
|
}
|
|
|
|
pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error>
|
|
where
|
|
RXDMA: crate::i2c::RxDma<T>,
|
|
{
|
|
if buffer.is_empty() {
|
|
self.read_internal(address, buffer, false)
|
|
} else {
|
|
self.read_dma_internal(address, buffer, false).await
|
|
}
|
|
}
|
|
|
|
pub async fn write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error>
|
|
where
|
|
TXDMA: super::TxDma<T>,
|
|
RXDMA: super::RxDma<T>,
|
|
{
|
|
if bytes.is_empty() {
|
|
self.write_internal(address, bytes, false)?;
|
|
} else {
|
|
self.write_dma_internal(address, bytes, true, true).await?;
|
|
}
|
|
|
|
if buffer.is_empty() {
|
|
self.read_internal(address, buffer, true)?;
|
|
} else {
|
|
self.read_dma_internal(address, buffer, true).await?;
|
|
}
|
|
|
|
Ok(())
|
|
}
|
|
|
|
// =========================
|
|
// Blocking public API
|
|
|
|
pub fn blocking_read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
|
|
self.read_internal(address, buffer, false)
|
|
// Automatic Stop
|
|
}
|
|
|
|
pub fn blocking_write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Error> {
|
|
self.write_internal(address, bytes, true)
|
|
}
|
|
|
|
pub fn blocking_write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Error> {
|
|
self.write_internal(address, bytes, false)?;
|
|
self.read_internal(address, buffer, true)
|
|
// Automatic Stop
|
|
}
|
|
|
|
pub fn blocking_write_vectored(&mut self, address: u8, bytes: &[&[u8]]) -> Result<(), Error> {
|
|
if bytes.is_empty() {
|
|
return Err(Error::ZeroLengthTransfer);
|
|
}
|
|
let first_length = bytes[0].len();
|
|
let last_slice_index = bytes.len() - 1;
|
|
|
|
// NOTE(unsafe) We have &mut self
|
|
unsafe {
|
|
Self::master_write(
|
|
address,
|
|
first_length.min(255),
|
|
Stop::Software,
|
|
(first_length > 255) || (last_slice_index != 0),
|
|
);
|
|
}
|
|
|
|
for (idx, slice) in bytes.iter().enumerate() {
|
|
let slice_len = slice.len();
|
|
let completed_chunks = slice_len / 255;
|
|
let total_chunks = if completed_chunks * 255 == slice_len {
|
|
completed_chunks
|
|
} else {
|
|
completed_chunks + 1
|
|
};
|
|
let last_chunk_idx = total_chunks.saturating_sub(1);
|
|
|
|
if idx != 0 {
|
|
// NOTE(unsafe) We have &mut self
|
|
unsafe {
|
|
Self::master_continue(slice_len.min(255), (idx != last_slice_index) || (slice_len > 255));
|
|
}
|
|
}
|
|
|
|
for (number, chunk) in slice.chunks(255).enumerate() {
|
|
if number != 0 {
|
|
// NOTE(unsafe) We have &mut self
|
|
unsafe {
|
|
Self::master_continue(chunk.len(), (number != last_chunk_idx) || (idx != last_slice_index));
|
|
}
|
|
}
|
|
|
|
for byte in chunk {
|
|
// Wait until we are allowed to send data
|
|
// (START has been ACKed or last byte when
|
|
// through)
|
|
self.wait_txe()?;
|
|
|
|
// Put byte on the wire
|
|
//self.i2c.txdr.write(|w| w.txdata().bits(*byte));
|
|
unsafe {
|
|
T::regs().txdr().write(|w| w.set_txdata(*byte));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
// Wait until the write finishes
|
|
self.wait_tc()?;
|
|
self.master_stop();
|
|
|
|
Ok(())
|
|
}
|
|
}
|
|
|
|
mod eh02 {
|
|
use super::*;
|
|
|
|
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::Read for I2c<'d, T> {
|
|
type Error = Error;
|
|
|
|
fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
|
|
self.blocking_read(address, buffer)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::Write for I2c<'d, T> {
|
|
type Error = Error;
|
|
|
|
fn write(&mut self, address: u8, bytes: &[u8]) -> Result<(), Self::Error> {
|
|
self.blocking_write(address, bytes)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, T> {
|
|
type Error = Error;
|
|
|
|
fn write_read(&mut self, address: u8, bytes: &[u8], buffer: &mut [u8]) -> Result<(), Self::Error> {
|
|
self.blocking_write_read(address, bytes, buffer)
|
|
}
|
|
}
|
|
}
|
|
|
|
/// I2C Stop Configuration
|
|
///
|
|
/// Peripheral options for generating the STOP condition
|
|
#[derive(Copy, Clone, PartialEq)]
|
|
enum Stop {
|
|
/// Software end mode: Must write register to generate STOP condition
|
|
Software,
|
|
/// Automatic end mode: A STOP condition is automatically generated once the
|
|
/// configured number of bytes have been transferred
|
|
Automatic,
|
|
}
|
|
|
|
impl Stop {
|
|
fn autoend(&self) -> i2c::vals::Autoend {
|
|
match self {
|
|
Stop::Software => i2c::vals::Autoend::SOFTWARE,
|
|
Stop::Automatic => i2c::vals::Autoend::AUTOMATIC,
|
|
}
|
|
}
|
|
}
|
|
|
|
struct Timings {
|
|
prescale: u8,
|
|
scll: u8,
|
|
sclh: u8,
|
|
sdadel: u8,
|
|
scldel: u8,
|
|
}
|
|
|
|
impl Timings {
|
|
fn new(i2cclk: Hertz, freq: Hertz) -> Self {
|
|
let i2cclk = i2cclk.0;
|
|
let freq = freq.0;
|
|
// Refer to RM0433 Rev 7 Figure 539 for setup and hold timing:
|
|
//
|
|
// t_I2CCLK = 1 / PCLK1
|
|
// t_PRESC = (PRESC + 1) * t_I2CCLK
|
|
// t_SCLL = (SCLL + 1) * t_PRESC
|
|
// t_SCLH = (SCLH + 1) * t_PRESC
|
|
//
|
|
// t_SYNC1 + t_SYNC2 > 4 * t_I2CCLK
|
|
// t_SCL ~= t_SYNC1 + t_SYNC2 + t_SCLL + t_SCLH
|
|
let ratio = i2cclk / freq;
|
|
|
|
// For the standard-mode configuration method, we must have a ratio of 4
|
|
// or higher
|
|
assert!(ratio >= 4, "The I2C PCLK must be at least 4 times the bus frequency!");
|
|
|
|
let (presc_reg, scll, sclh, sdadel, scldel) = if freq > 100_000 {
|
|
// Fast-mode (Fm) or Fast-mode Plus (Fm+)
|
|
// here we pick SCLL + 1 = 2 * (SCLH + 1)
|
|
|
|
// Prescaler, 384 ticks for sclh/scll. Round up then subtract 1
|
|
let presc_reg = ((ratio - 1) / 384) as u8;
|
|
// ratio < 1200 by pclk 120MHz max., therefore presc < 16
|
|
|
|
// Actual precale value selected
|
|
let presc = (presc_reg + 1) as u32;
|
|
|
|
let sclh = ((ratio / presc) - 3) / 3;
|
|
let scll = (2 * (sclh + 1)) - 1;
|
|
|
|
let (sdadel, scldel) = if freq > 400_000 {
|
|
// Fast-mode Plus (Fm+)
|
|
assert!(i2cclk >= 17_000_000); // See table in datsheet
|
|
|
|
let sdadel = i2cclk / 8_000_000 / presc;
|
|
let scldel = i2cclk / 4_000_000 / presc - 1;
|
|
|
|
(sdadel, scldel)
|
|
} else {
|
|
// Fast-mode (Fm)
|
|
assert!(i2cclk >= 8_000_000); // See table in datsheet
|
|
|
|
let sdadel = i2cclk / 4_000_000 / presc;
|
|
let scldel = i2cclk / 2_000_000 / presc - 1;
|
|
|
|
(sdadel, scldel)
|
|
};
|
|
|
|
(presc_reg, scll as u8, sclh as u8, sdadel as u8, scldel as u8)
|
|
} else {
|
|
// Standard-mode (Sm)
|
|
// here we pick SCLL = SCLH
|
|
assert!(i2cclk >= 2_000_000); // See table in datsheet
|
|
|
|
// Prescaler, 512 ticks for sclh/scll. Round up then
|
|
// subtract 1
|
|
let presc = (ratio - 1) / 512;
|
|
let presc_reg = cmp::min(presc, 15) as u8;
|
|
|
|
// Actual prescale value selected
|
|
let presc = (presc_reg + 1) as u32;
|
|
|
|
let sclh = ((ratio / presc) - 2) / 2;
|
|
let scll = sclh;
|
|
|
|
// Speed check
|
|
assert!(sclh < 256, "The I2C PCLK is too fast for this bus frequency!");
|
|
|
|
let sdadel = i2cclk / 2_000_000 / presc;
|
|
let scldel = i2cclk / 500_000 / presc - 1;
|
|
|
|
(presc_reg, scll as u8, sclh as u8, sdadel as u8, scldel as u8)
|
|
};
|
|
|
|
// Sanity check
|
|
assert!(presc_reg < 16);
|
|
|
|
// Keep values within reasonable limits for fast per_ck
|
|
let sdadel = cmp::max(sdadel, 2);
|
|
let scldel = cmp::max(scldel, 4);
|
|
|
|
//(presc_reg, scll, sclh, sdadel, scldel)
|
|
Self {
|
|
prescale: presc_reg,
|
|
scll,
|
|
sclh,
|
|
sdadel,
|
|
scldel,
|
|
}
|
|
}
|
|
}
|
|
|
|
#[cfg(feature = "unstable-traits")]
|
|
mod eh1 {
|
|
use super::super::{RxDma, TxDma};
|
|
use super::*;
|
|
|
|
impl embedded_hal_1::i2c::Error for Error {
|
|
fn kind(&self) -> embedded_hal_1::i2c::ErrorKind {
|
|
match *self {
|
|
Self::Bus => embedded_hal_1::i2c::ErrorKind::Bus,
|
|
Self::Arbitration => embedded_hal_1::i2c::ErrorKind::ArbitrationLoss,
|
|
Self::Nack => {
|
|
embedded_hal_1::i2c::ErrorKind::NoAcknowledge(embedded_hal_1::i2c::NoAcknowledgeSource::Unknown)
|
|
}
|
|
Self::Timeout => embedded_hal_1::i2c::ErrorKind::Other,
|
|
Self::Crc => embedded_hal_1::i2c::ErrorKind::Other,
|
|
Self::Overrun => embedded_hal_1::i2c::ErrorKind::Overrun,
|
|
Self::ZeroLengthTransfer => embedded_hal_1::i2c::ErrorKind::Other,
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance, TXDMA: TxDma<T>, RXDMA: RxDma<T>> embedded_hal_1::i2c::ErrorType for I2c<'d, T, TXDMA, RXDMA> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d, T: Instance, TXDMA: TxDma<T>, RXDMA: RxDma<T>> embedded_hal_1::i2c::blocking::I2c
|
|
for I2c<'d, T, TXDMA, RXDMA>
|
|
{
|
|
fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
|
|
self.blocking_read(address, buffer)
|
|
}
|
|
|
|
fn write(&mut self, address: u8, buffer: &[u8]) -> Result<(), Self::Error> {
|
|
self.blocking_write(address, buffer)
|
|
}
|
|
|
|
fn write_iter<B>(&mut self, _address: u8, _bytes: B) -> Result<(), Self::Error>
|
|
where
|
|
B: IntoIterator<Item = u8>,
|
|
{
|
|
todo!();
|
|
}
|
|
|
|
fn write_iter_read<B>(&mut self, _address: u8, _bytes: B, _buffer: &mut [u8]) -> Result<(), Self::Error>
|
|
where
|
|
B: IntoIterator<Item = u8>,
|
|
{
|
|
todo!();
|
|
}
|
|
|
|
fn write_read(&mut self, address: u8, wr_buffer: &[u8], rd_buffer: &mut [u8]) -> Result<(), Self::Error> {
|
|
self.blocking_write_read(address, wr_buffer, rd_buffer)
|
|
}
|
|
|
|
fn transaction<'a>(
|
|
&mut self,
|
|
_address: u8,
|
|
_operations: &mut [embedded_hal_1::i2c::blocking::Operation<'a>],
|
|
) -> Result<(), Self::Error> {
|
|
todo!();
|
|
}
|
|
|
|
fn transaction_iter<'a, O>(&mut self, _address: u8, _operations: O) -> Result<(), Self::Error>
|
|
where
|
|
O: IntoIterator<Item = embedded_hal_1::i2c::blocking::Operation<'a>>,
|
|
{
|
|
todo!();
|
|
}
|
|
}
|
|
}
|
|
|
|
cfg_if::cfg_if! {
|
|
if #[cfg(all(feature = "unstable-traits", feature = "nightly"))] {
|
|
use super::{RxDma, TxDma};
|
|
use core::future::Future;
|
|
|
|
impl<'d, T: Instance, TXDMA: TxDma<T>, RXDMA: RxDma<T>> embedded_hal_async::i2c::I2c
|
|
for I2c<'d, T, TXDMA, RXDMA>
|
|
{
|
|
type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
|
|
fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Self::ReadFuture<'a> {
|
|
self.read(address, buffer)
|
|
}
|
|
|
|
type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Self::WriteFuture<'a> {
|
|
self.write(address, bytes)
|
|
}
|
|
|
|
type WriteReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
|
|
fn write_read<'a>(
|
|
&'a mut self,
|
|
address: u8,
|
|
bytes: &'a [u8],
|
|
buffer: &'a mut [u8],
|
|
) -> Self::WriteReadFuture<'a> {
|
|
self.write_read(address, bytes, buffer)
|
|
}
|
|
|
|
type TransactionFuture<'a, 'b> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a, 'b: 'a;
|
|
|
|
fn transaction<'a, 'b>(
|
|
&'a mut self,
|
|
address: u8,
|
|
operations: &'a mut [embedded_hal_async::i2c::Operation<'b>],
|
|
) -> Self::TransactionFuture<'a, 'b> {
|
|
let _ = address;
|
|
let _ = operations;
|
|
async move { todo!() }
|
|
}
|
|
}
|
|
}
|
|
}
|