609 lines
21 KiB
Rust
609 lines
21 KiB
Rust
//! Digital Camera Interface (DCMI)
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use core::future::poll_fn;
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use core::marker::PhantomData;
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use core::task::Poll;
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use embassy_hal_internal::{into_ref, PeripheralRef};
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use embassy_sync::waitqueue::AtomicWaker;
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use crate::dma::Transfer;
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use crate::gpio::sealed::AFType;
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use crate::gpio::Speed;
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use crate::interrupt::typelevel::Interrupt;
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use crate::{interrupt, Peripheral};
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/// Interrupt handler.
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pub struct InterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
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unsafe fn on_interrupt() {
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let ris = crate::pac::DCMI.ris().read();
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if ris.err_ris() {
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trace!("DCMI IRQ: Error.");
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crate::pac::DCMI.ier().modify(|ier| ier.set_err_ie(false));
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}
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if ris.ovr_ris() {
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trace!("DCMI IRQ: Overrun.");
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crate::pac::DCMI.ier().modify(|ier| ier.set_ovr_ie(false));
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}
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if ris.frame_ris() {
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trace!("DCMI IRQ: Frame captured.");
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crate::pac::DCMI.ier().modify(|ier| ier.set_frame_ie(false));
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}
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STATE.waker.wake();
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}
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}
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/// The level on the VSync pin when the data is not valid on the parallel interface.
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#[allow(missing_docs)]
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#[derive(Clone, Copy, PartialEq)]
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pub enum VSyncDataInvalidLevel {
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Low,
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High,
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}
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/// The level on the VSync pin when the data is not valid on the parallel interface.
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#[allow(missing_docs)]
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#[derive(Clone, Copy, PartialEq)]
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pub enum HSyncDataInvalidLevel {
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Low,
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High,
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}
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#[derive(Clone, Copy, PartialEq)]
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#[allow(missing_docs)]
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pub enum PixelClockPolarity {
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RisingEdge,
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FallingEdge,
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}
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struct State {
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waker: AtomicWaker,
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}
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impl State {
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const fn new() -> State {
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State {
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waker: AtomicWaker::new(),
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}
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}
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}
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static STATE: State = State::new();
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/// DCMI error.
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#[derive(Debug, Eq, PartialEq, Copy, Clone)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub enum Error {
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/// Overrun error: the hardware generated data faster than we could read it.
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Overrun,
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/// Internal peripheral error.
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PeripheralError,
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}
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/// DCMI configuration.
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#[non_exhaustive]
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pub struct Config {
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/// VSYNC level.
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pub vsync_level: VSyncDataInvalidLevel,
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/// HSYNC level.
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pub hsync_level: HSyncDataInvalidLevel,
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/// PIXCLK polarity.
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pub pixclk_polarity: PixelClockPolarity,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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vsync_level: VSyncDataInvalidLevel::High,
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hsync_level: HSyncDataInvalidLevel::Low,
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pixclk_polarity: PixelClockPolarity::RisingEdge,
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}
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}
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}
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macro_rules! config_pins {
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($($pin:ident),*) => {
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into_ref!($($pin),*);
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critical_section::with(|_| {
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$(
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$pin.set_as_af($pin.af_num(), AFType::Input);
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$pin.set_speed(Speed::VeryHigh);
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)*
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})
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};
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}
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/// DCMI driver.
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pub struct Dcmi<'d, T: Instance, Dma: FrameDma<T>> {
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inner: PeripheralRef<'d, T>,
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dma: PeripheralRef<'d, Dma>,
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}
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impl<'d, T, Dma> Dcmi<'d, T, Dma>
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where
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T: Instance,
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Dma: FrameDma<T>,
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{
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/// Create a new DCMI driver with 8 data bits.
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pub fn new_8bit(
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peri: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = Dma> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
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d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
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d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
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d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
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d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
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d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
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v_sync: impl Peripheral<P = impl VSyncPin<T>> + 'd,
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h_sync: impl Peripheral<P = impl HSyncPin<T>> + 'd,
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pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, dma);
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config_pins!(d0, d1, d2, d3, d4, d5, d6, d7);
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config_pins!(v_sync, h_sync, pixclk);
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Self::new_inner(peri, dma, config, false, 0b00)
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}
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/// Create a new DCMI driver with 10 data bits.
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pub fn new_10bit(
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peri: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = Dma> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
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d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
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d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
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d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
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d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
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d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
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d8: impl Peripheral<P = impl D8Pin<T>> + 'd,
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d9: impl Peripheral<P = impl D9Pin<T>> + 'd,
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v_sync: impl Peripheral<P = impl VSyncPin<T>> + 'd,
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h_sync: impl Peripheral<P = impl HSyncPin<T>> + 'd,
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pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, dma);
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config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9);
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config_pins!(v_sync, h_sync, pixclk);
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Self::new_inner(peri, dma, config, false, 0b01)
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}
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/// Create a new DCMI driver with 12 data bits.
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pub fn new_12bit(
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peri: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = Dma> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
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d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
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d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
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d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
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d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
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d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
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d8: impl Peripheral<P = impl D8Pin<T>> + 'd,
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d9: impl Peripheral<P = impl D9Pin<T>> + 'd,
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d10: impl Peripheral<P = impl D10Pin<T>> + 'd,
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d11: impl Peripheral<P = impl D11Pin<T>> + 'd,
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v_sync: impl Peripheral<P = impl VSyncPin<T>> + 'd,
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h_sync: impl Peripheral<P = impl HSyncPin<T>> + 'd,
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pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, dma);
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config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11);
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config_pins!(v_sync, h_sync, pixclk);
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Self::new_inner(peri, dma, config, false, 0b10)
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}
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/// Create a new DCMI driver with 14 data bits.
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pub fn new_14bit(
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peri: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = Dma> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
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d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
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d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
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d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
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d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
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d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
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d8: impl Peripheral<P = impl D8Pin<T>> + 'd,
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d9: impl Peripheral<P = impl D9Pin<T>> + 'd,
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d10: impl Peripheral<P = impl D10Pin<T>> + 'd,
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d11: impl Peripheral<P = impl D11Pin<T>> + 'd,
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d12: impl Peripheral<P = impl D12Pin<T>> + 'd,
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d13: impl Peripheral<P = impl D13Pin<T>> + 'd,
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v_sync: impl Peripheral<P = impl VSyncPin<T>> + 'd,
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h_sync: impl Peripheral<P = impl HSyncPin<T>> + 'd,
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pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, dma);
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config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13);
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config_pins!(v_sync, h_sync, pixclk);
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Self::new_inner(peri, dma, config, false, 0b11)
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}
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/// Create a new DCMI driver with 8 data bits, with embedded synchronization.
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pub fn new_es_8bit(
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peri: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = Dma> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
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d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
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d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
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d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
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d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
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d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
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pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, dma);
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config_pins!(d0, d1, d2, d3, d4, d5, d6, d7);
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config_pins!(pixclk);
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Self::new_inner(peri, dma, config, true, 0b00)
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}
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/// Create a new DCMI driver with 10 data bits, with embedded synchronization.
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pub fn new_es_10bit(
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peri: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = Dma> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
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d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
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d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
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d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
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d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
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d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
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d8: impl Peripheral<P = impl D8Pin<T>> + 'd,
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d9: impl Peripheral<P = impl D9Pin<T>> + 'd,
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pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, dma);
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config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9);
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config_pins!(pixclk);
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Self::new_inner(peri, dma, config, true, 0b01)
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}
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/// Create a new DCMI driver with 12 data bits, with embedded synchronization.
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pub fn new_es_12bit(
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peri: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = Dma> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
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d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
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d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
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d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
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d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
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d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
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d8: impl Peripheral<P = impl D8Pin<T>> + 'd,
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d9: impl Peripheral<P = impl D9Pin<T>> + 'd,
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d10: impl Peripheral<P = impl D10Pin<T>> + 'd,
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d11: impl Peripheral<P = impl D11Pin<T>> + 'd,
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pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, dma);
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config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11);
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config_pins!(pixclk);
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Self::new_inner(peri, dma, config, true, 0b10)
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}
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/// Create a new DCMI driver with 14 data bits, with embedded synchronization.
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pub fn new_es_14bit(
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peri: impl Peripheral<P = T> + 'd,
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dma: impl Peripheral<P = Dma> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
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d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
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d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
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d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
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d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
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d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
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d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
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d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
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d8: impl Peripheral<P = impl D8Pin<T>> + 'd,
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d9: impl Peripheral<P = impl D9Pin<T>> + 'd,
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d10: impl Peripheral<P = impl D10Pin<T>> + 'd,
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d11: impl Peripheral<P = impl D11Pin<T>> + 'd,
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d12: impl Peripheral<P = impl D12Pin<T>> + 'd,
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d13: impl Peripheral<P = impl D13Pin<T>> + 'd,
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pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(peri, dma);
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config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13);
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config_pins!(pixclk);
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Self::new_inner(peri, dma, config, true, 0b11)
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}
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fn new_inner(
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peri: PeripheralRef<'d, T>,
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dma: PeripheralRef<'d, Dma>,
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config: Config,
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use_embedded_synchronization: bool,
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edm: u8,
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) -> Self {
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T::enable_and_reset();
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peri.regs().cr().modify(|r| {
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r.set_cm(true); // disable continuous mode (snapshot mode)
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r.set_ess(use_embedded_synchronization);
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r.set_pckpol(config.pixclk_polarity == PixelClockPolarity::RisingEdge);
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r.set_vspol(config.vsync_level == VSyncDataInvalidLevel::High);
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r.set_hspol(config.hsync_level == HSyncDataInvalidLevel::High);
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r.set_fcrc(0x00); // capture every frame
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r.set_edm(edm); // extended data mode
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});
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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Self { inner: peri, dma }
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}
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fn toggle(enable: bool) {
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crate::pac::DCMI.cr().modify(|r| {
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r.set_enable(enable);
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r.set_capture(enable);
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})
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}
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fn enable_irqs() {
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crate::pac::DCMI.ier().modify(|r| {
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r.set_err_ie(true);
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r.set_ovr_ie(true);
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r.set_frame_ie(true);
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});
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}
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fn clear_interrupt_flags() {
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crate::pac::DCMI.icr().write(|r| {
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r.set_ovr_isc(true);
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r.set_err_isc(true);
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r.set_frame_isc(true);
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})
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}
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/// This method starts the capture and finishes when both the dma transfer and DCMI finish the frame transfer.
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/// The implication is that the input buffer size must be exactly the size of the captured frame.
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///
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/// Note that when `buffer.len() > 0xffff` the capture future requires some real-time guarantees to be upheld
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/// (must be polled fast enough so the buffers get switched before data is overwritten).
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/// It is therefore recommended that it is run on higher priority executor.
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pub async fn capture(&mut self, buffer: &mut [u32]) -> Result<(), Error> {
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if buffer.len() <= 0xffff {
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return self.capture_small(buffer).await;
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} else {
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return self.capture_giant(buffer).await;
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}
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}
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async fn capture_small(&mut self, buffer: &mut [u32]) -> Result<(), Error> {
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let r = self.inner.regs();
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let src = r.dr().as_ptr() as *mut u32;
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let request = self.dma.request();
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let dma_read = unsafe { Transfer::new_read(&mut self.dma, request, src, buffer, Default::default()) };
|
|
|
|
Self::clear_interrupt_flags();
|
|
Self::enable_irqs();
|
|
|
|
Self::toggle(true);
|
|
|
|
let result = poll_fn(|cx| {
|
|
STATE.waker.register(cx.waker());
|
|
|
|
let ris = crate::pac::DCMI.ris().read();
|
|
if ris.err_ris() {
|
|
crate::pac::DCMI.icr().write(|r| r.set_err_isc(true));
|
|
Poll::Ready(Err(Error::PeripheralError))
|
|
} else if ris.ovr_ris() {
|
|
crate::pac::DCMI.icr().write(|r| r.set_ovr_isc(true));
|
|
Poll::Ready(Err(Error::Overrun))
|
|
} else if ris.frame_ris() {
|
|
crate::pac::DCMI.icr().write(|r| r.set_frame_isc(true));
|
|
Poll::Ready(Ok(()))
|
|
} else {
|
|
Poll::Pending
|
|
}
|
|
});
|
|
|
|
let (_, result) = embassy_futures::join::join(dma_read, result).await;
|
|
|
|
Self::toggle(false);
|
|
|
|
result
|
|
}
|
|
|
|
#[cfg(not(dma))]
|
|
async fn capture_giant(&mut self, _buffer: &mut [u32]) -> Result<(), Error> {
|
|
panic!("capturing to buffers larger than 0xffff is only supported on DMA for now, not on BDMA or GPDMA.");
|
|
}
|
|
|
|
#[cfg(dma)]
|
|
async fn capture_giant(&mut self, buffer: &mut [u32]) -> Result<(), Error> {
|
|
use crate::dma::TransferOptions;
|
|
|
|
let data_len = buffer.len();
|
|
let chunk_estimate = data_len / 0xffff;
|
|
|
|
let mut chunks = chunk_estimate + 1;
|
|
while data_len % chunks != 0 {
|
|
chunks += 1;
|
|
}
|
|
|
|
let chunk_size = data_len / chunks;
|
|
|
|
let mut remaining_chunks = chunks - 2;
|
|
|
|
let mut m0ar = buffer.as_mut_ptr();
|
|
let mut m1ar = unsafe { buffer.as_mut_ptr().add(chunk_size) };
|
|
|
|
let channel = &mut self.dma;
|
|
let request = channel.request();
|
|
|
|
let r = self.inner.regs();
|
|
let src = r.dr().as_ptr() as *mut u32;
|
|
|
|
let mut transfer = unsafe {
|
|
crate::dma::DoubleBuffered::new_read(
|
|
&mut self.dma,
|
|
request,
|
|
src,
|
|
m0ar,
|
|
m1ar,
|
|
chunk_size,
|
|
TransferOptions::default(),
|
|
)
|
|
};
|
|
|
|
let mut last_chunk_set_for_transfer = false;
|
|
let mut buffer0_last_accessible = false;
|
|
let dma_result = poll_fn(|cx| {
|
|
transfer.set_waker(cx.waker());
|
|
|
|
let buffer0_currently_accessible = transfer.is_buffer0_accessible();
|
|
|
|
// check if the accessible buffer changed since last poll
|
|
if buffer0_last_accessible == buffer0_currently_accessible {
|
|
return Poll::Pending;
|
|
}
|
|
buffer0_last_accessible = !buffer0_last_accessible;
|
|
|
|
if remaining_chunks != 0 {
|
|
if remaining_chunks % 2 == 0 && buffer0_currently_accessible {
|
|
m0ar = unsafe { m0ar.add(2 * chunk_size) };
|
|
unsafe { transfer.set_buffer0(m0ar) }
|
|
remaining_chunks -= 1;
|
|
} else if !buffer0_currently_accessible {
|
|
m1ar = unsafe { m1ar.add(2 * chunk_size) };
|
|
unsafe { transfer.set_buffer1(m1ar) };
|
|
remaining_chunks -= 1;
|
|
}
|
|
} else {
|
|
if buffer0_currently_accessible {
|
|
unsafe { transfer.set_buffer0(buffer.as_mut_ptr()) }
|
|
} else {
|
|
unsafe { transfer.set_buffer1(buffer.as_mut_ptr()) }
|
|
}
|
|
if last_chunk_set_for_transfer {
|
|
transfer.request_stop();
|
|
return Poll::Ready(());
|
|
}
|
|
last_chunk_set_for_transfer = true;
|
|
}
|
|
Poll::Pending
|
|
});
|
|
|
|
Self::clear_interrupt_flags();
|
|
Self::enable_irqs();
|
|
|
|
let result = poll_fn(|cx| {
|
|
STATE.waker.register(cx.waker());
|
|
|
|
let ris = crate::pac::DCMI.ris().read();
|
|
if ris.err_ris() {
|
|
crate::pac::DCMI.icr().write(|r| r.set_err_isc(true));
|
|
Poll::Ready(Err(Error::PeripheralError))
|
|
} else if ris.ovr_ris() {
|
|
crate::pac::DCMI.icr().write(|r| r.set_ovr_isc(true));
|
|
Poll::Ready(Err(Error::Overrun))
|
|
} else if ris.frame_ris() {
|
|
crate::pac::DCMI.icr().write(|r| r.set_frame_isc(true));
|
|
Poll::Ready(Ok(()))
|
|
} else {
|
|
Poll::Pending
|
|
}
|
|
});
|
|
|
|
Self::toggle(true);
|
|
|
|
let (_, result) = embassy_futures::join::join(dma_result, result).await;
|
|
|
|
Self::toggle(false);
|
|
|
|
result
|
|
}
|
|
}
|
|
|
|
mod sealed {
|
|
pub trait Instance: crate::rcc::RccPeripheral {
|
|
fn regs(&self) -> crate::pac::dcmi::Dcmi;
|
|
}
|
|
}
|
|
|
|
/// DCMI instance.
|
|
pub trait Instance: sealed::Instance + 'static {
|
|
/// Interrupt for this instance.
|
|
type Interrupt: interrupt::typelevel::Interrupt;
|
|
}
|
|
|
|
pin_trait!(D0Pin, Instance);
|
|
pin_trait!(D1Pin, Instance);
|
|
pin_trait!(D2Pin, Instance);
|
|
pin_trait!(D3Pin, Instance);
|
|
pin_trait!(D4Pin, Instance);
|
|
pin_trait!(D5Pin, Instance);
|
|
pin_trait!(D6Pin, Instance);
|
|
pin_trait!(D7Pin, Instance);
|
|
pin_trait!(D8Pin, Instance);
|
|
pin_trait!(D9Pin, Instance);
|
|
pin_trait!(D10Pin, Instance);
|
|
pin_trait!(D11Pin, Instance);
|
|
pin_trait!(D12Pin, Instance);
|
|
pin_trait!(D13Pin, Instance);
|
|
pin_trait!(HSyncPin, Instance);
|
|
pin_trait!(VSyncPin, Instance);
|
|
pin_trait!(PixClkPin, Instance);
|
|
|
|
// allow unused as U5 sources do not contain interrupt nor dma data
|
|
#[allow(unused)]
|
|
macro_rules! impl_peripheral {
|
|
($inst:ident, $irq:ident) => {
|
|
impl sealed::Instance for crate::peripherals::$inst {
|
|
fn regs(&self) -> crate::pac::dcmi::Dcmi {
|
|
crate::pac::$inst
|
|
}
|
|
}
|
|
|
|
impl Instance for crate::peripherals::$inst {
|
|
type Interrupt = crate::interrupt::typelevel::$irq;
|
|
}
|
|
};
|
|
}
|
|
|
|
foreach_interrupt! {
|
|
($inst:ident, dcmi, $block:ident, GLOBAL, $irq:ident) => {
|
|
impl_peripheral!($inst, $irq);
|
|
};
|
|
}
|
|
|
|
dma_trait!(FrameDma, Instance);
|