Change the UART RX FIFO depth from 1/8 to 7/8. This should allow for
buffered receipt of uart data with a lower IRQ load.
The PL011 fifo is pretty smart about the fifo, it has an automatic
timeout (which triggers an interrupt) of about 4 characters worth of
time, so setting this threshold doesn't affect the behavior of receipt
of a partially filled fifo.
This should not have any affect on the DMA mode, as the DMA will
generally drain the fifo as data becomes available.
The constraint for the fifo threshold should be determined by expected
interrupt latency. The IRQ needs to be able to drain the fifo before it
fills. As such, the proper threshold depends on system design and data
rate. At full speed (7.8 Mbaud), the remaining 8 characters will come
in in about 10us, which is probably insufficient. But, the time is quite
adequate at lower speeds.
They're heavily spamming logs for HIL tests, and I don't believe
they're valuable now that the thing they helped debug in their young
age is now solid and mature.
we'll need access to the pin io bank registers for an upcoming fix, and
having both `io` and `io_bank` or similar can get confusing quickly.
rename `io` to `gpio` to avoid this, and also match the type while there.
- Move typelevel interrupts to a special-purpose mod: `embassy_xx::interrupt::typelevel`.
- Reexport the PAC interrupt enum in `embassy_xx::interrupt`.
This has a few advantages:
- The `embassy_xx::interrupt` module is now more "standard".
- It works with `cortex-m` functions for manipulating interrupts, for example.
- It works with RTIC.
- the interrupt enum allows holding value that can be "any interrupt at runtime", this can't be done with typelevel irqs.
- When "const-generics on enums" is stable, we can remove the typelevel interrupts without disruptive changes to `embassy_xx::interrupt`.
this reports errors at the same location the blocking uart would, which
works out to being mostly exact (except in the case of overruns, where
one extra character is dropped). this is actually easier than going
nuclear in the case of errors and nuking both the buffer contents and
the rx fifo, both of which are things we'd have to do in addition to
what's added here, and neither are needed for correctness.
