antonello.contini
724e1a34e5
simpler configuration
2025-02-25 21:37:01 +01:00
antonello.contini
51085a5e94
let user set external i2s clock frequency
2025-02-25 21:21:23 +01:00
antonello.contini
f1c7e388e6
do not use pllsrc for i2s; added field for plli2ssrc selection
2025-02-25 19:59:57 +01:00
vinsynth
6ec72c0af0
set PLLI2SM and plli2s_src f423
2025-02-02 18:53:06 -05:00
vinsynth
ce04cf8340
set PLLI2S M and SRC for f4 chips which support it
2025-02-02 18:12:34 -05:00
Bing Wen
52ab015fac
Add new
2024-11-27 12:23:13 +08:00
Bing Wen
8eaa3c8fd3
Add new feature to enable overclocking
2024-11-26 12:46:20 +08:00
Alexandros Liarokapis
2b7e76efe9
Fix dma nvic issues on dual core lines
...
This commit addresses #3256 by disabling dma NVIC interrupt enablement at startup.
Instead, per-channel NVIC interrupt enablement is now done with the rest of the dma channel configuration.
This ensures that each core will only handle the interrupts of the DMA channels that it uses.
2024-08-17 16:54:41 +03:00
Dario Nieuwenhuis
5ecc9b805d
Merge pull request #2829 from aurelj/stm32-rcc-hsi
...
stm32: ensure the core runs on HSI clock while setting up rcc
2024-05-21 22:06:24 +00:00
Joël Schulz-Ansres
4c55931b6a
Remove redundant dsi_phy: None from rcc
2024-05-02 14:58:38 +02:00
Joël Schulz-Ansres
9fe50a7639
Add stm32 dsihost driver
2024-05-02 13:43:42 +02:00
eZio Pan
d9e59e8e42
low power for h5
2024-04-28 00:33:02 +08:00
Aurélien Jacobs
10ee1c1ae8
stm32: ensure the core runs on HSI clock while setting up rcc
2024-04-16 23:36:47 +02:00
Dario Nieuwenhuis
95234cddba
stm32: autogenerate mux config for all chips.
2024-03-01 23:54:37 +01:00
Dario Nieuwenhuis
c83ab20526
stm32: update metapac.
2024-02-26 03:02:58 +01:00
Dario Nieuwenhuis
1860e22693
stm32/rcc: unify f0, f1, f3.
2024-02-14 17:24:20 +01:00
