Martin Algesten
4743501172
Move PLL2/3 config to before PLL
2025-01-24 10:06:32 +01:00
Martin Algesten
3ba94c0ab3
Fix init order of set_prediv1src
2025-01-24 09:36:11 +01:00
Martin Algesten
c72d9ec859
Review fixes
2025-01-24 09:16:24 +01:00
Martin Algesten
9a159a8db0
Full RCC support for STM32F107
2025-01-16 15:31:41 +01:00
elagil
eba8089601
chore: fix build
2025-01-03 18:18:00 +01:00
Fabian Wolter
4b31639dca
STM32F0 fix using HSI48 as SYSCLK on devices with CRS
...
Fixes #3651
2024-12-14 23:32:08 +01:00
Bing Wen
d0340ad297
Fix & Revert
2024-11-27 12:33:32 +08:00
Bing Wen
52ab015fac
Add new
2024-11-27 12:23:13 +08:00
Bing Wen
8eaa3c8fd3
Add new feature to enable overclocking
2024-11-26 12:46:20 +08:00
Alexandros Liarokapis
2b7e76efe9
Fix dma nvic issues on dual core lines
...
This commit addresses #3256 by disabling dma NVIC interrupt enablement at startup.
Instead, per-channel NVIC interrupt enablement is now done with the rest of the dma channel configuration.
This ensures that each core will only handle the interrupts of the DMA channels that it uses.
2024-08-17 16:54:41 +03:00
Jan Špaček
368893c9cb
Emit cargo:rustc-check-cfg instructions from build.rs
2024-05-30 18:28:29 +02:00
Dario Nieuwenhuis
c46172acac
stm32: remove pointer-to-pointer-to-registers.
...
in chiptool pacs the register block struct is already a pointer, so
using pointers to it is redundant.
2024-05-30 13:07:18 +02:00
Aurélien Jacobs
ec6cfc1f21
stm32: ensure the core runs on HSI clock while setting up rcc
2024-05-27 17:31:29 +02:00
Dario Nieuwenhuis
6f44d7a9df
stm32: update metapac. Adds U5 LPDMA, fixes ADC_COMMONs.
2024-04-29 20:52:27 +02:00
Dario Nieuwenhuis
95234cddba
stm32: autogenerate mux config for all chips.
2024-03-01 23:54:37 +01:00
Dario Nieuwenhuis
c83ab20526
stm32: update metapac.
2024-02-26 03:02:58 +01:00
Eli Orona
2dfd66b7c4
🤦
2024-02-25 16:25:42 -08:00
Eli Orona
7dbae799dc
Rust FMT
2024-02-25 16:24:52 -08:00
Eli Orona
c23b59bdc8
Add pll1_p_mul_2 clock.
2024-02-25 16:12:32 -08:00
Eli Orona
e79d2dd756
Move to internal mod and re-export the enums
2024-02-24 12:54:58 -08:00
Eli Orona
2ee9b37373
Move to a single Mux Struct.
2024-02-20 17:54:35 -08:00
Eli Orona
e99ef49611
Move to auto-generated based system.
2024-02-16 19:57:00 -08:00
Eli Orona
c99c4a01a9
Update f013.rs
2024-02-16 16:47:38 -08:00
Eli Orona
7592e8be6e
Fix build
2024-02-16 16:45:58 -08:00
Eli Orona
77739faaeb
Rustfmt
2024-02-16 16:42:19 -08:00
Eli Orona
370db9fb06
Update f013.rs
...
Add stm32f398
2024-02-16 16:39:23 -08:00
Eli Orona
d7623c7929
Remove extraneous , in cfg
2024-02-15 23:20:35 -08:00
Eli Orona
d28ba1d606
rustfmt
2024-02-15 23:16:17 -08:00
Eli Orona
56b345c722
Clean up register setting
2024-02-15 23:12:18 -08:00
Eli Orona
4408c169a5
Fix cfg lines
2024-02-15 22:55:11 -08:00
Eli Orona
029d6383b5
Rust fmt and fix build.
2024-02-15 20:02:25 -08:00
Eli Orona
169f1ce928
I believe that this enables the PLL clock input to different TIMs for the STM32F3xx Series of chips.
2024-02-15 19:50:42 -08:00
Dario Nieuwenhuis
1860e22693
stm32/rcc: unify f0, f1, f3.
2024-02-14 17:24:20 +01:00
