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Author SHA1 Message Date
Frostie314159
67c9cc2c4b
Merge branch 'embassy-rs:main' into ticker_send_sync 2024-03-31 20:48:05 +02:00
Sebastian Goll
6564fab092 Merge remote-tracking branch 'upstream/main' into i2c-async-transaction 2024-03-31 19:13:42 +02:00
Frostie314159
a2f9aa592e
Made Ticker::next Send+Sync. 2024-03-31 15:07:01 +02:00
Alex Moon
f8a6007e1c Semaphore synchronization primitive 
This provides both a "greedy" and "fair" async semaphore implementation.
 2024-03-30 22:25:41 -04:00
Dario Nieuwenhuis
6634cc90bc
Merge pull request #2754 from UPB-FILS-MA/alexandruradovici-patch-1 
Fix a typo in embassy-sync
 2024-03-30 21:41:03 +00:00
Alexandru Radovici
a38cbbdc59
fix typo 2024-03-30 22:36:30 +02:00
Sebastian Goll
1b505bf18e Merge remote-tracking branch 'upstream/main' into i2c-async-transaction 2024-03-28 22:39:52 +01:00
Dario Nieuwenhuis
81cf9d1143
Merge pull request #2295 from Frostie314159/reset-at-after 
Introduce `reset_{at|after}` functions for ticker.
 2024-03-28 19:04:26 +00:00
Frostie314159
2ea1040e07
Adjusted behavior. 2024-03-28 19:41:50 +01:00
schmettow
f10ee07a90
Update embassy_in_the_wild.adoc 
corrected link to Ystudio project
 2024-03-28 14:35:24 +01:00
Dario Nieuwenhuis
393de9e19f
Merge pull request #2744 from cschuhen/feature/bxcan_use_fdcan_api 
Synchronise the feature sets and API between BXCAN and FDCAN.
 2024-03-28 00:10:11 +00:00
Corey Schuhen
25618cd93d RTR fix. 2024-03-28 09:53:30 +10:00
Corey Schuhen
a9f0c8c3a9 Fixes for no-time. 2024-03-28 09:32:13 +10:00
Corey Schuhen
8d43fb4da4 CAN: Use the same testing code for BXCAN and FDCAN h/w. 2024-03-28 09:32:13 +10:00
Corey Schuhen
2217b80278 CAN: Unify API's between BXCAN and FDCAN. Use Envelope for all read methods instead of a tuple sometimes. 2024-03-28 09:32:13 +10:00
Corey Schuhen
f5daa50a7b BXCAN: Add struct that combines Buffered RX and Buffered TX. 2024-03-28 09:32:13 +10:00
Corey Schuhen
41b7e4a434 BXCAN: Create TxMode in order to support buffered TX. 2024-03-28 09:32:13 +10:00
Corey Schuhen
26c739c2f9 BXCAN: Create RxMode enum and move reader methods into it, laying foundations for different Rx buffering modes. 2024-03-28 09:32:13 +10:00
Corey Schuhen
3bdaad39e8 BXCAN: Register access into new Registers struct. 2024-03-28 09:32:13 +10:00
Corey Schuhen
32065d7719 BXCAN: Cut out more that wasn't required from BXCAN crate. 2024-03-28 09:32:08 +10:00
Corey Schuhen
fcfcfce400 CAN: Move some FDCAN definitions into a module to share with BXCAN. 2024-03-28 09:30:58 +10:00
Dario Nieuwenhuis
8f6c07c775
Merge pull request #2745 from de-vri-es/bxcan-keep-rtr-flag 
embassy_stm32: Preseve the RTR flag in messages.
 2024-03-27 22:35:43 +00:00
Sebastian Goll
3133201724 Merge remote-tracking branch 'upstream/main' into i2c-async-transaction 2024-03-27 18:58:59 +01:00
Maarten de Vries
c059062627 embassy_stm32: Preseve the RTR flag in messages. 2024-03-27 16:10:37 +01:00
Dario Nieuwenhuis
a678b4850c
Merge pull request #2739 from adri326/adri326/nodma-embedded-io 
Provide embedded_io impls for Uart with and without Dma
 2024-03-27 14:47:19 +00:00
Dario Nieuwenhuis
289c5edb9b
Merge pull request #2738 from eZioPan/h5-lse-low-drive 
stm32 H5: LSE low drive mode is not functional
 2024-03-27 14:34:22 +00:00
Emilie Burgun
e3ef7cd99f Document why embedded_io::Read cannot be implemented for the base Uart 2024-03-27 11:10:16 +01:00
Sebastian Goll
bb5fcce0a0 Use named imports within function to make code easier to read 2024-03-27 10:42:38 +01:00
Sebastian Goll
b52e9a60eb Add missing check for empty buffer in asynchronous read_write() 2024-03-27 10:39:33 +01:00
Sebastian Goll
13636556d9 Mark shared data structure as dead_code for I2C v2 branch 2024-03-27 01:41:13 +01:00
Sebastian Goll
0cfb65abc2 Add transaction stub to I2C v2 2024-03-27 01:36:06 +01:00
Sebastian Goll
54d7d49513 Refactor DMA implementation of I2C v1, clarify flow of code 2024-03-27 01:07:42 +01:00
Sebastian Goll
7e44db099c Move FrameOptions and related function to module itself 2024-03-27 00:35:30 +01:00
Sebastian Goll
b299266cd2 It is not necessary to enable interrupts before registering waker 2024-03-27 00:32:06 +01:00
Sebastian Goll
2e2986c67b It is not necessary to wait for SB and MSL sequentially 2024-03-27 00:32:06 +01:00
Sebastian Goll
c1175bf7d8 It is not necessary to wait for STOP to be fully generated 2024-03-27 00:32:06 +01:00
Sebastian Goll
accec7a840 Implement asynchronous transaction for I2C v1 2024-03-27 00:32:06 +01:00
Sebastian Goll
9c00a40e73 Extract frame options generation into iterator to reuse in async 2024-03-26 22:53:14 +01:00
Sebastian Goll
0885c102d3 Refactor async I2C transfers to use frame options 2024-03-26 22:53:14 +01:00
Sebastian Goll
746ded94b1 Fix minor typos 2024-03-26 22:53:14 +01:00
schmettow
82046c4691
Added YLab project to "in the wild" 
YLab uses Embassy
 2024-03-26 22:26:44 +01:00
eZio Pan
cf11d28d62 stm32 H5: LSE low drive mode is not functional 2024-03-27 00:55:44 +08:00
Emilie Burgun
1acc34bfaa Remove the need for TxDma to be a DMA channel in the blocking UartTx impl 2024-03-26 17:45:38 +01:00
Dario Nieuwenhuis
f3a0bcb15e
Merge pull request #2737 from adri326/adri326/add-iosv-option 
Add a config option to make the VDDIO2 supply line valid
 2024-03-26 16:29:45 +00:00
Emilie Burgun
402def86ee Remove ad-hoc fixes for setting the IOSV bit to true 2024-03-26 17:27:02 +01:00
Emilie Burgun
ca998c170f Missing half of the implementation detail comment 2024-03-26 16:33:41 +01:00
Emilie Burgun
64964bd614 Add a config option to make the VDDIO2 supply line valid 
On STM32L4[7-A]xx, STM32L5xxx and STM32U5xxx chips, the GPIOG[2..15] pins are only available
once the IOSV bit has been set in PWR->CR2 (U5 chips have the bit in a funkier register).

This is meant to allow the user to have control over this power supply, so the GPIOG pins
are initially insulated, until the user wishes to un-insulate them (or something like that?).
For most applications, though, the VDDIO2 is connected to the VDD line, and this behavior only
gets in the way and causes confusing issues.

This submission adds an option in `embassy_stm32::Config`, called `enable_independent_io_supply`,
which simply enables the IOSV bit. It is only available on chips for which I could find a mention
of IOSV (STM32L4 and STM32L5) or IO2SV (STM32U5).
 2024-03-26 16:22:05 +01:00
eZio Pan
6b2e15e318 stm32 CORDIC: exclude stm32u5a 2024-03-26 15:06:06 +08:00
Dario Nieuwenhuis
cdd1c671e9
Merge pull request #2707 from barafael/barafael/minor_clippy_lints_rp 
fix minor clippy lints in embassy_rp
 2024-03-25 14:31:52 +00:00
Rafael Bachmann
e139a4e076 fix: CI 2024-03-25 15:09:41 +01:00