Merge pull request #3539 from embassy-rs/update-nrf-pac
Update nrf-pac.
This commit is contained in:
		
						commit
						fe79af5614
					
				| @ -17,7 +17,7 @@ log = [ "dep:log" ] | |||||||
| defmt = { version = "0.3", optional = true } | defmt = { version = "0.3", optional = true } | ||||||
| log = { version = "0.4.14", optional = true } | log = { version = "0.4.14", optional = true } | ||||||
| 
 | 
 | ||||||
| nrf-pac = { git = "https://github.com/embassy-rs/nrf-pac", rev = "875a29629cc1c87aae00cfea647a956b3807d8be" } | nrf-pac = { git = "https://github.com/embassy-rs/nrf-pac", rev = "12e2461859acb0bfea9b2ef5cd73f1283c139ac0" } | ||||||
| cortex-m = "0.7.7" | cortex-m = "0.7.7" | ||||||
| 
 | 
 | ||||||
| embassy-time = { version = "0.3.1", path = "../embassy-time" } | embassy-time = { version = "0.3.1", path = "../embassy-time" } | ||||||
|  | |||||||
| @ -136,7 +136,7 @@ embedded-hal-async = { version = "1.0" } | |||||||
| embedded-io = { version = "0.6.0" } | embedded-io = { version = "0.6.0" } | ||||||
| embedded-io-async = { version = "0.6.1" } | embedded-io-async = { version = "0.6.1" } | ||||||
| 
 | 
 | ||||||
| nrf-pac = { git = "https://github.com/embassy-rs/nrf-pac", rev = "875a29629cc1c87aae00cfea647a956b3807d8be" } | nrf-pac = { git = "https://github.com/embassy-rs/nrf-pac", rev = "12e2461859acb0bfea9b2ef5cd73f1283c139ac0" } | ||||||
| 
 | 
 | ||||||
| defmt = { version = "0.3", optional = true } | defmt = { version = "0.3", optional = true } | ||||||
| bitflags = "2.4.2" | bitflags = "2.4.2" | ||||||
|  | |||||||
| @ -146,11 +146,11 @@ impl_pin!(P0_31, 0, 31); | |||||||
| impl_radio!(RADIO, RADIO, RADIO); | impl_radio!(RADIO, RADIO, RADIO); | ||||||
| 
 | 
 | ||||||
| embassy_hal_internal::interrupt_mod!( | embassy_hal_internal::interrupt_mod!( | ||||||
|     POWER_CLOCK, |     CLOCK_POWER, | ||||||
|     RADIO, |     RADIO, | ||||||
|     UART0, |     UART0, | ||||||
|     SPI0_TWI0, |     TWISPI0, | ||||||
|     SPI1_TWI1, |     TWISPI1, | ||||||
|     GPIOTE, |     GPIOTE, | ||||||
|     ADC, |     ADC, | ||||||
|     TIMER0, |     TIMER0, | ||||||
| @ -160,7 +160,7 @@ embassy_hal_internal::interrupt_mod!( | |||||||
|     TEMP, |     TEMP, | ||||||
|     RNG, |     RNG, | ||||||
|     ECB, |     ECB, | ||||||
|     CCM_AAR, |     AAR_CCM, | ||||||
|     WDT, |     WDT, | ||||||
|     RTC1, |     RTC1, | ||||||
|     QDEC, |     QDEC, | ||||||
|  | |||||||
| @ -138,15 +138,15 @@ embassy_hal_internal::peripherals! { | |||||||
|     EGU1, |     EGU1, | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
| impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); | impl_uarte!(UARTE0, UARTE0, UARTE0); | ||||||
| 
 | 
 | ||||||
| impl_spim!(SPI0, SPIM0, SPIM0_SPIS0_SPI0); | impl_spim!(SPI0, SPIM0, SPI0); | ||||||
| 
 | 
 | ||||||
| impl_spis!(SPI0, SPIS0, SPIM0_SPIS0_SPI0); | impl_spis!(SPI0, SPIS0, SPI0); | ||||||
| 
 | 
 | ||||||
| impl_twim!(TWI0, TWIM0, TWIM0_TWIS0_TWI0); | impl_twim!(TWI0, TWIM0, TWI0); | ||||||
| 
 | 
 | ||||||
| impl_twis!(TWI0, TWIS0, TWIM0_TWIS0_TWI0); | impl_twis!(TWI0, TWIS0, TWI0); | ||||||
| 
 | 
 | ||||||
| impl_qdec!(QDEC, QDEC, QDEC); | impl_qdec!(QDEC, QDEC, QDEC); | ||||||
| 
 | 
 | ||||||
| @ -218,15 +218,15 @@ impl_saadc_input!(P0_05, ANALOG_INPUT3); | |||||||
| 
 | 
 | ||||||
| impl_radio!(RADIO, RADIO, RADIO); | impl_radio!(RADIO, RADIO, RADIO); | ||||||
| 
 | 
 | ||||||
| impl_egu!(EGU0, EGU0, SWI0_EGU0); | impl_egu!(EGU0, EGU0, EGU0_SWI0); | ||||||
| impl_egu!(EGU1, EGU1, SWI1_EGU1); | impl_egu!(EGU1, EGU1, EGU1_SWI1); | ||||||
| 
 | 
 | ||||||
| embassy_hal_internal::interrupt_mod!( | embassy_hal_internal::interrupt_mod!( | ||||||
|     POWER_CLOCK, |     CLOCK_POWER, | ||||||
|     RADIO, |     RADIO, | ||||||
|     UARTE0_UART0, |     UARTE0, | ||||||
|     TWIM0_TWIS0_TWI0, |     TWI0, | ||||||
|     SPIM0_SPIS0_SPI0, |     SPI0, | ||||||
|     GPIOTE, |     GPIOTE, | ||||||
|     SAADC, |     SAADC, | ||||||
|     TIMER0, |     TIMER0, | ||||||
| @ -236,12 +236,12 @@ embassy_hal_internal::interrupt_mod!( | |||||||
|     TEMP, |     TEMP, | ||||||
|     RNG, |     RNG, | ||||||
|     ECB, |     ECB, | ||||||
|     CCM_AAR, |     AAR_CCM, | ||||||
|     WDT, |     WDT, | ||||||
|     RTC1, |     RTC1, | ||||||
|     QDEC, |     QDEC, | ||||||
|     SWI0_EGU0, |     EGU0_SWI0, | ||||||
|     SWI1_EGU1, |     EGU1_SWI1, | ||||||
|     SWI2, |     SWI2, | ||||||
|     SWI3, |     SWI3, | ||||||
|     SWI4, |     SWI4, | ||||||
|  | |||||||
| @ -144,15 +144,15 @@ embassy_hal_internal::peripherals! { | |||||||
|     EGU1, |     EGU1, | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
| impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); | impl_uarte!(UARTE0, UARTE0, UARTE0); | ||||||
| 
 | 
 | ||||||
| impl_spim!(SPI0, SPIM0, SPIM0_SPIS0_SPI0); | impl_spim!(SPI0, SPIM0, SPI0); | ||||||
| 
 | 
 | ||||||
| impl_spis!(SPI0, SPIS0, SPIM0_SPIS0_SPI0); | impl_spis!(SPI0, SPIS0, SPI0); | ||||||
| 
 | 
 | ||||||
| impl_twim!(TWI0, TWIM0, TWIM0_TWIS0_TWI0); | impl_twim!(TWI0, TWIM0, TWI0); | ||||||
| 
 | 
 | ||||||
| impl_twis!(TWI0, TWIS0, TWIM0_TWIS0_TWI0); | impl_twis!(TWI0, TWIS0, TWI0); | ||||||
| 
 | 
 | ||||||
| impl_pwm!(PWM0, PWM0, PWM0); | impl_pwm!(PWM0, PWM0, PWM0); | ||||||
| 
 | 
 | ||||||
| @ -244,15 +244,15 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7); | |||||||
| 
 | 
 | ||||||
| impl_radio!(RADIO, RADIO, RADIO); | impl_radio!(RADIO, RADIO, RADIO); | ||||||
| 
 | 
 | ||||||
| impl_egu!(EGU0, EGU0, SWI0_EGU0); | impl_egu!(EGU0, EGU0, EGU0_SWI0); | ||||||
| impl_egu!(EGU1, EGU1, SWI1_EGU1); | impl_egu!(EGU1, EGU1, EGU1_SWI1); | ||||||
| 
 | 
 | ||||||
| embassy_hal_internal::interrupt_mod!( | embassy_hal_internal::interrupt_mod!( | ||||||
|     POWER_CLOCK, |     CLOCK_POWER, | ||||||
|     RADIO, |     RADIO, | ||||||
|     UARTE0_UART0, |     UARTE0, | ||||||
|     TWIM0_TWIS0_TWI0, |     TWI0, | ||||||
|     SPIM0_SPIS0_SPI0, |     SPI0, | ||||||
|     GPIOTE, |     GPIOTE, | ||||||
|     SAADC, |     SAADC, | ||||||
|     TIMER0, |     TIMER0, | ||||||
| @ -262,13 +262,13 @@ embassy_hal_internal::interrupt_mod!( | |||||||
|     TEMP, |     TEMP, | ||||||
|     RNG, |     RNG, | ||||||
|     ECB, |     ECB, | ||||||
|     CCM_AAR, |     AAR_CCM, | ||||||
|     WDT, |     WDT, | ||||||
|     RTC1, |     RTC1, | ||||||
|     QDEC, |     QDEC, | ||||||
|     COMP, |     COMP, | ||||||
|     SWI0_EGU0, |     EGU0_SWI0, | ||||||
|     SWI1_EGU1, |     EGU1_SWI1, | ||||||
|     SWI2, |     SWI2, | ||||||
|     SWI3, |     SWI3, | ||||||
|     SWI4, |     SWI4, | ||||||
|  | |||||||
| @ -27,8 +27,8 @@ embassy_hal_internal::peripherals! { | |||||||
|     UARTE0, |     UARTE0, | ||||||
| 
 | 
 | ||||||
|     // SPI/TWI
 |     // SPI/TWI
 | ||||||
|     TWISPI0, |     TWI0_SPI1, | ||||||
|     SPI1, |     SPI0, | ||||||
| 
 | 
 | ||||||
|     // SAADC
 |     // SAADC
 | ||||||
|     SAADC, |     SAADC, | ||||||
| @ -144,17 +144,17 @@ embassy_hal_internal::peripherals! { | |||||||
|     EGU1, |     EGU1, | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
| impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); | impl_uarte!(UARTE0, UARTE0, UARTE0); | ||||||
| 
 | 
 | ||||||
| impl_spim!(TWISPI0, SPIM0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0); | impl_spim!(SPI0, SPIM0, SPI0); | ||||||
| impl_spim!(SPI1, SPIM1, SPIM1_SPIS1_SPI1); | impl_spim!(TWI0_SPI1, SPIM1, TWI0_SPI1); | ||||||
| 
 | 
 | ||||||
| impl_spis!(TWISPI0, SPIS0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0); | impl_spis!(SPI0, SPIS0, SPI0); | ||||||
| impl_spis!(SPI1, SPIS1, SPIM1_SPIS1_SPI1); | impl_spis!(TWI0_SPI1, SPIS1, TWI0_SPI1); | ||||||
| 
 | 
 | ||||||
| impl_twim!(TWISPI0, TWIM0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0); | impl_twim!(TWI0_SPI1, TWIM0, TWI0_SPI1); | ||||||
| 
 | 
 | ||||||
| impl_twis!(TWISPI0, TWIS0, TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0); | impl_twis!(TWI0_SPI1, TWIS0, TWI0_SPI1); | ||||||
| 
 | 
 | ||||||
| impl_pwm!(PWM0, PWM0, PWM0); | impl_pwm!(PWM0, PWM0, PWM0); | ||||||
| 
 | 
 | ||||||
| @ -246,15 +246,15 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7); | |||||||
| 
 | 
 | ||||||
| impl_radio!(RADIO, RADIO, RADIO); | impl_radio!(RADIO, RADIO, RADIO); | ||||||
| 
 | 
 | ||||||
| impl_egu!(EGU0, EGU0, SWI0_EGU0); | impl_egu!(EGU0, EGU0, EGU0_SWI0); | ||||||
| impl_egu!(EGU1, EGU1, SWI1_EGU1); | impl_egu!(EGU1, EGU1, EGU1_SWI1); | ||||||
| 
 | 
 | ||||||
| embassy_hal_internal::interrupt_mod!( | embassy_hal_internal::interrupt_mod!( | ||||||
|     POWER_CLOCK, |     CLOCK_POWER, | ||||||
|     RADIO, |     RADIO, | ||||||
|     UARTE0_UART0, |     UARTE0, | ||||||
|     TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0, |     TWI0_SPI1, | ||||||
|     SPIM1_SPIS1_SPI1, |     SPI0, | ||||||
|     GPIOTE, |     GPIOTE, | ||||||
|     SAADC, |     SAADC, | ||||||
|     TIMER0, |     TIMER0, | ||||||
| @ -264,13 +264,13 @@ embassy_hal_internal::interrupt_mod!( | |||||||
|     TEMP, |     TEMP, | ||||||
|     RNG, |     RNG, | ||||||
|     ECB, |     ECB, | ||||||
|     CCM_AAR, |     AAR_CCM, | ||||||
|     WDT, |     WDT, | ||||||
|     RTC1, |     RTC1, | ||||||
|     QDEC, |     QDEC, | ||||||
|     COMP, |     COMP, | ||||||
|     SWI0_EGU0, |     EGU0_SWI0, | ||||||
|     SWI1_EGU1, |     EGU1_SWI1, | ||||||
|     SWI2, |     SWI2, | ||||||
|     SWI3, |     SWI3, | ||||||
|     SWI4, |     SWI4, | ||||||
|  | |||||||
| @ -145,19 +145,19 @@ embassy_hal_internal::peripherals! { | |||||||
| 
 | 
 | ||||||
| impl_usb!(USBD, USBD, USBD); | impl_usb!(USBD, USBD, USBD); | ||||||
| 
 | 
 | ||||||
| impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); | impl_uarte!(UARTE0, UARTE0, UARTE0); | ||||||
| 
 | 
 | ||||||
| impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | impl_spim!(TWISPI0, SPIM0, TWISPI0); | ||||||
| impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | impl_spim!(TWISPI1, SPIM1, TWISPI1); | ||||||
| 
 | 
 | ||||||
| impl_spis!(TWISPI0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | impl_spis!(TWISPI0, SPIS0, TWISPI0); | ||||||
| impl_spis!(TWISPI1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | impl_spis!(TWISPI1, SPIS1, TWISPI1); | ||||||
| 
 | 
 | ||||||
| impl_twim!(TWISPI0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | impl_twim!(TWISPI0, TWIM0, TWISPI0); | ||||||
| impl_twim!(TWISPI1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | impl_twim!(TWISPI1, TWIM1, TWISPI1); | ||||||
| 
 | 
 | ||||||
| impl_twis!(TWISPI0, TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | impl_twis!(TWISPI0, TWIS0, TWISPI0); | ||||||
| impl_twis!(TWISPI1, TWIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | impl_twis!(TWISPI1, TWIS1, TWISPI1); | ||||||
| 
 | 
 | ||||||
| impl_timer!(TIMER0, TIMER0, TIMER0); | impl_timer!(TIMER0, TIMER0, TIMER0); | ||||||
| impl_timer!(TIMER1, TIMER1, TIMER1); | impl_timer!(TIMER1, TIMER1, TIMER1); | ||||||
| @ -237,19 +237,19 @@ impl_ppi_channel!(PPI_CH31, 31 => static); | |||||||
| 
 | 
 | ||||||
| impl_radio!(RADIO, RADIO, RADIO); | impl_radio!(RADIO, RADIO, RADIO); | ||||||
| 
 | 
 | ||||||
| impl_egu!(EGU0, EGU0, SWI0_EGU0); | impl_egu!(EGU0, EGU0, EGU0_SWI0); | ||||||
| impl_egu!(EGU1, EGU1, SWI1_EGU1); | impl_egu!(EGU1, EGU1, EGU1_SWI1); | ||||||
| impl_egu!(EGU2, EGU2, SWI2_EGU2); | impl_egu!(EGU2, EGU2, EGU2_SWI2); | ||||||
| impl_egu!(EGU3, EGU3, SWI3_EGU3); | impl_egu!(EGU3, EGU3, EGU3_SWI3); | ||||||
| impl_egu!(EGU4, EGU4, SWI4_EGU4); | impl_egu!(EGU4, EGU4, EGU4_SWI4); | ||||||
| impl_egu!(EGU5, EGU5, SWI5_EGU5); | impl_egu!(EGU5, EGU5, EGU5_SWI5); | ||||||
| 
 | 
 | ||||||
| embassy_hal_internal::interrupt_mod!( | embassy_hal_internal::interrupt_mod!( | ||||||
|     POWER_CLOCK, |     CLOCK_POWER, | ||||||
|     RADIO, |     RADIO, | ||||||
|     UARTE0_UART0, |     UARTE0, | ||||||
|     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0, |     TWISPI0, | ||||||
|     SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1, |     TWISPI1, | ||||||
|     GPIOTE, |     GPIOTE, | ||||||
|     TIMER0, |     TIMER0, | ||||||
|     TIMER1, |     TIMER1, | ||||||
| @ -258,17 +258,17 @@ embassy_hal_internal::interrupt_mod!( | |||||||
|     TEMP, |     TEMP, | ||||||
|     RNG, |     RNG, | ||||||
|     ECB, |     ECB, | ||||||
|     CCM_AAR, |     AAR_CCM, | ||||||
|     WDT, |     WDT, | ||||||
|     RTC1, |     RTC1, | ||||||
|     QDEC, |     QDEC, | ||||||
|     COMP, |     COMP, | ||||||
|     SWI0_EGU0, |     EGU0_SWI0, | ||||||
|     SWI1_EGU1, |     EGU1_SWI1, | ||||||
|     SWI2_EGU2, |     EGU2_SWI2, | ||||||
|     SWI3_EGU3, |     EGU3_SWI3, | ||||||
|     SWI4_EGU4, |     EGU4_SWI4, | ||||||
|     SWI5_EGU5, |     EGU5_SWI5, | ||||||
|     TIMER3, |     TIMER3, | ||||||
|     USBD, |     USBD, | ||||||
| ); | ); | ||||||
|  | |||||||
| @ -163,21 +163,21 @@ embassy_hal_internal::peripherals! { | |||||||
|     EGU5, |     EGU5, | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
| impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); | impl_uarte!(UARTE0, UARTE0, UARTE0); | ||||||
| 
 | 
 | ||||||
| impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | impl_spim!(TWISPI0, SPIM0, TWISPI0); | ||||||
| impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | impl_spim!(TWISPI1, SPIM1, TWISPI1); | ||||||
| impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2); | impl_spim!(SPI2, SPIM2, SPI2); | ||||||
| 
 | 
 | ||||||
| impl_spis!(TWISPI0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | impl_spis!(TWISPI0, SPIS0, TWISPI0); | ||||||
| impl_spis!(TWISPI1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | impl_spis!(TWISPI1, SPIS1, TWISPI1); | ||||||
| impl_spis!(SPI2, SPIS2, SPIM2_SPIS2_SPI2); | impl_spis!(SPI2, SPIS2, SPI2); | ||||||
| 
 | 
 | ||||||
| impl_twim!(TWISPI0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | impl_twim!(TWISPI0, TWIM0, TWISPI0); | ||||||
| impl_twim!(TWISPI1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | impl_twim!(TWISPI1, TWIM1, TWISPI1); | ||||||
| 
 | 
 | ||||||
| impl_twis!(TWISPI0, TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | impl_twis!(TWISPI0, TWIS0, TWISPI0); | ||||||
| impl_twis!(TWISPI1, TWIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | impl_twis!(TWISPI1, TWIS1, TWISPI1); | ||||||
| 
 | 
 | ||||||
| impl_pwm!(PWM0, PWM0, PWM0); | impl_pwm!(PWM0, PWM0, PWM0); | ||||||
| impl_pwm!(PWM1, PWM1, PWM1); | impl_pwm!(PWM1, PWM1, PWM1); | ||||||
| @ -277,19 +277,19 @@ impl_i2s!(I2S, I2S, I2S); | |||||||
| 
 | 
 | ||||||
| impl_radio!(RADIO, RADIO, RADIO); | impl_radio!(RADIO, RADIO, RADIO); | ||||||
| 
 | 
 | ||||||
| impl_egu!(EGU0, EGU0, SWI0_EGU0); | impl_egu!(EGU0, EGU0, EGU0_SWI0); | ||||||
| impl_egu!(EGU1, EGU1, SWI1_EGU1); | impl_egu!(EGU1, EGU1, EGU1_SWI1); | ||||||
| impl_egu!(EGU2, EGU2, SWI2_EGU2); | impl_egu!(EGU2, EGU2, EGU2_SWI2); | ||||||
| impl_egu!(EGU3, EGU3, SWI3_EGU3); | impl_egu!(EGU3, EGU3, EGU3_SWI3); | ||||||
| impl_egu!(EGU4, EGU4, SWI4_EGU4); | impl_egu!(EGU4, EGU4, EGU4_SWI4); | ||||||
| impl_egu!(EGU5, EGU5, SWI5_EGU5); | impl_egu!(EGU5, EGU5, EGU5_SWI5); | ||||||
| 
 | 
 | ||||||
| embassy_hal_internal::interrupt_mod!( | embassy_hal_internal::interrupt_mod!( | ||||||
|     POWER_CLOCK, |     CLOCK_POWER, | ||||||
|     RADIO, |     RADIO, | ||||||
|     UARTE0_UART0, |     UARTE0, | ||||||
|     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0, |     TWISPI0, | ||||||
|     SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1, |     TWISPI1, | ||||||
|     NFCT, |     NFCT, | ||||||
|     GPIOTE, |     GPIOTE, | ||||||
|     SAADC, |     SAADC, | ||||||
| @ -300,17 +300,17 @@ embassy_hal_internal::interrupt_mod!( | |||||||
|     TEMP, |     TEMP, | ||||||
|     RNG, |     RNG, | ||||||
|     ECB, |     ECB, | ||||||
|     CCM_AAR, |     AAR_CCM, | ||||||
|     WDT, |     WDT, | ||||||
|     RTC1, |     RTC1, | ||||||
|     QDEC, |     QDEC, | ||||||
|     COMP_LPCOMP, |     COMP_LPCOMP, | ||||||
|     SWI0_EGU0, |     EGU0_SWI0, | ||||||
|     SWI1_EGU1, |     EGU1_SWI1, | ||||||
|     SWI2_EGU2, |     EGU2_SWI2, | ||||||
|     SWI3_EGU3, |     EGU3_SWI3, | ||||||
|     SWI4_EGU4, |     EGU4_SWI4, | ||||||
|     SWI5_EGU5, |     EGU5_SWI5, | ||||||
|     TIMER3, |     TIMER3, | ||||||
|     TIMER4, |     TIMER4, | ||||||
|     PWM0, |     PWM0, | ||||||
| @ -318,8 +318,8 @@ embassy_hal_internal::interrupt_mod!( | |||||||
|     MWU, |     MWU, | ||||||
|     PWM1, |     PWM1, | ||||||
|     PWM2, |     PWM2, | ||||||
|     SPIM2_SPIS2_SPI2, |     SPI2, | ||||||
|     RTC2, |     RTC2, | ||||||
|     FPU, |  | ||||||
|     I2S, |     I2S, | ||||||
|  |     FPU, | ||||||
| ); | ); | ||||||
|  | |||||||
| @ -185,23 +185,23 @@ embassy_hal_internal::peripherals! { | |||||||
| 
 | 
 | ||||||
| impl_usb!(USBD, USBD, USBD); | impl_usb!(USBD, USBD, USBD); | ||||||
| 
 | 
 | ||||||
| impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); | impl_uarte!(UARTE0, UARTE0, UARTE0); | ||||||
| impl_uarte!(UARTE1, UARTE1, UARTE1); | impl_uarte!(UARTE1, UARTE1, UARTE1); | ||||||
| 
 | 
 | ||||||
| impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | impl_spim!(TWISPI0, SPIM0, TWISPI0); | ||||||
| impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | impl_spim!(TWISPI1, SPIM1, TWISPI1); | ||||||
| impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2); | impl_spim!(SPI2, SPIM2, SPI2); | ||||||
| impl_spim!(SPI3, SPIM3, SPIM3); | impl_spim!(SPI3, SPIM3, SPIM3); | ||||||
| 
 | 
 | ||||||
| impl_spis!(TWISPI0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | impl_spis!(TWISPI0, SPIS0, TWISPI0); | ||||||
| impl_spis!(TWISPI1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | impl_spis!(TWISPI1, SPIS1, TWISPI1); | ||||||
| impl_spis!(SPI2, SPIS2, SPIM2_SPIS2_SPI2); | impl_spis!(SPI2, SPIS2, SPI2); | ||||||
| 
 | 
 | ||||||
| impl_twim!(TWISPI0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | impl_twim!(TWISPI0, TWIM0, TWISPI0); | ||||||
| impl_twim!(TWISPI1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | impl_twim!(TWISPI1, TWIM1, TWISPI1); | ||||||
| 
 | 
 | ||||||
| impl_twis!(TWISPI0, TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | impl_twis!(TWISPI0, TWIS0, TWISPI0); | ||||||
| impl_twis!(TWISPI1, TWIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | impl_twis!(TWISPI1, TWIS1, TWISPI1); | ||||||
| 
 | 
 | ||||||
| impl_pwm!(PWM0, PWM0, PWM0); | impl_pwm!(PWM0, PWM0, PWM0); | ||||||
| impl_pwm!(PWM1, PWM1, PWM1); | impl_pwm!(PWM1, PWM1, PWM1); | ||||||
| @ -319,19 +319,19 @@ impl_i2s!(I2S, I2S, I2S); | |||||||
| 
 | 
 | ||||||
| impl_radio!(RADIO, RADIO, RADIO); | impl_radio!(RADIO, RADIO, RADIO); | ||||||
| 
 | 
 | ||||||
| impl_egu!(EGU0, EGU0, SWI0_EGU0); | impl_egu!(EGU0, EGU0, EGU0_SWI0); | ||||||
| impl_egu!(EGU1, EGU1, SWI1_EGU1); | impl_egu!(EGU1, EGU1, EGU1_SWI1); | ||||||
| impl_egu!(EGU2, EGU2, SWI2_EGU2); | impl_egu!(EGU2, EGU2, EGU2_SWI2); | ||||||
| impl_egu!(EGU3, EGU3, SWI3_EGU3); | impl_egu!(EGU3, EGU3, EGU3_SWI3); | ||||||
| impl_egu!(EGU4, EGU4, SWI4_EGU4); | impl_egu!(EGU4, EGU4, EGU4_SWI4); | ||||||
| impl_egu!(EGU5, EGU5, SWI5_EGU5); | impl_egu!(EGU5, EGU5, EGU5_SWI5); | ||||||
| 
 | 
 | ||||||
| embassy_hal_internal::interrupt_mod!( | embassy_hal_internal::interrupt_mod!( | ||||||
|     POWER_CLOCK, |     CLOCK_POWER, | ||||||
|     RADIO, |     RADIO, | ||||||
|     UARTE0_UART0, |     UARTE0, | ||||||
|     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0, |     TWISPI0, | ||||||
|     SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1, |     TWISPI1, | ||||||
|     NFCT, |     NFCT, | ||||||
|     GPIOTE, |     GPIOTE, | ||||||
|     SAADC, |     SAADC, | ||||||
| @ -342,17 +342,17 @@ embassy_hal_internal::interrupt_mod!( | |||||||
|     TEMP, |     TEMP, | ||||||
|     RNG, |     RNG, | ||||||
|     ECB, |     ECB, | ||||||
|     CCM_AAR, |     AAR_CCM, | ||||||
|     WDT, |     WDT, | ||||||
|     RTC1, |     RTC1, | ||||||
|     QDEC, |     QDEC, | ||||||
|     COMP_LPCOMP, |     COMP_LPCOMP, | ||||||
|     SWI0_EGU0, |     EGU0_SWI0, | ||||||
|     SWI1_EGU1, |     EGU1_SWI1, | ||||||
|     SWI2_EGU2, |     EGU2_SWI2, | ||||||
|     SWI3_EGU3, |     EGU3_SWI3, | ||||||
|     SWI4_EGU4, |     EGU4_SWI4, | ||||||
|     SWI5_EGU5, |     EGU5_SWI5, | ||||||
|     TIMER3, |     TIMER3, | ||||||
|     TIMER4, |     TIMER4, | ||||||
|     PWM0, |     PWM0, | ||||||
| @ -360,12 +360,12 @@ embassy_hal_internal::interrupt_mod!( | |||||||
|     MWU, |     MWU, | ||||||
|     PWM1, |     PWM1, | ||||||
|     PWM2, |     PWM2, | ||||||
|     SPIM2_SPIS2_SPI2, |     SPI2, | ||||||
|     RTC2, |     RTC2, | ||||||
|  |     I2S, | ||||||
|     FPU, |     FPU, | ||||||
|     USBD, |     USBD, | ||||||
|     UARTE1, |     UARTE1, | ||||||
|     PWM3, |     PWM3, | ||||||
|     SPIM3, |     SPIM3, | ||||||
|     I2S, |  | ||||||
| ); | ); | ||||||
|  | |||||||
| @ -188,23 +188,23 @@ embassy_hal_internal::peripherals! { | |||||||
| 
 | 
 | ||||||
| impl_usb!(USBD, USBD, USBD); | impl_usb!(USBD, USBD, USBD); | ||||||
| 
 | 
 | ||||||
| impl_uarte!(UARTE0, UARTE0, UARTE0_UART0); | impl_uarte!(UARTE0, UARTE0, UARTE0); | ||||||
| impl_uarte!(UARTE1, UARTE1, UARTE1); | impl_uarte!(UARTE1, UARTE1, UARTE1); | ||||||
| 
 | 
 | ||||||
| impl_spim!(TWISPI0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | impl_spim!(TWISPI0, SPIM0, TWISPI0); | ||||||
| impl_spim!(TWISPI1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | impl_spim!(TWISPI1, SPIM1, TWISPI1); | ||||||
| impl_spim!(SPI2, SPIM2, SPIM2_SPIS2_SPI2); | impl_spim!(SPI2, SPIM2, SPI2); | ||||||
| impl_spim!(SPI3, SPIM3, SPIM3); | impl_spim!(SPI3, SPIM3, SPIM3); | ||||||
| 
 | 
 | ||||||
| impl_spis!(TWISPI0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | impl_spis!(TWISPI0, SPIS0, TWISPI0); | ||||||
| impl_spis!(TWISPI1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | impl_spis!(TWISPI1, SPIS1, TWISPI1); | ||||||
| impl_spis!(SPI2, SPIS2, SPIM2_SPIS2_SPI2); | impl_spis!(SPI2, SPIS2, SPI2); | ||||||
| 
 | 
 | ||||||
| impl_twim!(TWISPI0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | impl_twim!(TWISPI0, TWIM0, TWISPI0); | ||||||
| impl_twim!(TWISPI1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | impl_twim!(TWISPI1, TWIM1, TWISPI1); | ||||||
| 
 | 
 | ||||||
| impl_twis!(TWISPI0, TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0); | impl_twis!(TWISPI0, TWIS0, TWISPI0); | ||||||
| impl_twis!(TWISPI1, TWIS1, SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1); | impl_twis!(TWISPI1, TWIS1, TWISPI1); | ||||||
| 
 | 
 | ||||||
| impl_pwm!(PWM0, PWM0, PWM0); | impl_pwm!(PWM0, PWM0, PWM0); | ||||||
| impl_pwm!(PWM1, PWM1, PWM1); | impl_pwm!(PWM1, PWM1, PWM1); | ||||||
| @ -324,19 +324,19 @@ impl_i2s!(I2S, I2S, I2S); | |||||||
| 
 | 
 | ||||||
| impl_radio!(RADIO, RADIO, RADIO); | impl_radio!(RADIO, RADIO, RADIO); | ||||||
| 
 | 
 | ||||||
| impl_egu!(EGU0, EGU0, SWI0_EGU0); | impl_egu!(EGU0, EGU0, EGU0_SWI0); | ||||||
| impl_egu!(EGU1, EGU1, SWI1_EGU1); | impl_egu!(EGU1, EGU1, EGU1_SWI1); | ||||||
| impl_egu!(EGU2, EGU2, SWI2_EGU2); | impl_egu!(EGU2, EGU2, EGU2_SWI2); | ||||||
| impl_egu!(EGU3, EGU3, SWI3_EGU3); | impl_egu!(EGU3, EGU3, EGU3_SWI3); | ||||||
| impl_egu!(EGU4, EGU4, SWI4_EGU4); | impl_egu!(EGU4, EGU4, EGU4_SWI4); | ||||||
| impl_egu!(EGU5, EGU5, SWI5_EGU5); | impl_egu!(EGU5, EGU5, EGU5_SWI5); | ||||||
| 
 | 
 | ||||||
| embassy_hal_internal::interrupt_mod!( | embassy_hal_internal::interrupt_mod!( | ||||||
|     POWER_CLOCK, |     CLOCK_POWER, | ||||||
|     RADIO, |     RADIO, | ||||||
|     UARTE0_UART0, |     UARTE0, | ||||||
|     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0, |     TWISPI0, | ||||||
|     SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1, |     TWISPI1, | ||||||
|     NFCT, |     NFCT, | ||||||
|     GPIOTE, |     GPIOTE, | ||||||
|     SAADC, |     SAADC, | ||||||
| @ -347,17 +347,17 @@ embassy_hal_internal::interrupt_mod!( | |||||||
|     TEMP, |     TEMP, | ||||||
|     RNG, |     RNG, | ||||||
|     ECB, |     ECB, | ||||||
|     CCM_AAR, |     AAR_CCM, | ||||||
|     WDT, |     WDT, | ||||||
|     RTC1, |     RTC1, | ||||||
|     QDEC, |     QDEC, | ||||||
|     COMP_LPCOMP, |     COMP_LPCOMP, | ||||||
|     SWI0_EGU0, |     EGU0_SWI0, | ||||||
|     SWI1_EGU1, |     EGU1_SWI1, | ||||||
|     SWI2_EGU2, |     EGU2_SWI2, | ||||||
|     SWI3_EGU3, |     EGU3_SWI3, | ||||||
|     SWI4_EGU4, |     EGU4_SWI4, | ||||||
|     SWI5_EGU5, |     EGU5_SWI5, | ||||||
|     TIMER3, |     TIMER3, | ||||||
|     TIMER4, |     TIMER4, | ||||||
|     PWM0, |     PWM0, | ||||||
| @ -365,8 +365,9 @@ embassy_hal_internal::interrupt_mod!( | |||||||
|     MWU, |     MWU, | ||||||
|     PWM1, |     PWM1, | ||||||
|     PWM2, |     PWM2, | ||||||
|     SPIM2_SPIS2_SPI2, |     SPI2, | ||||||
|     RTC2, |     RTC2, | ||||||
|  |     I2S, | ||||||
|     FPU, |     FPU, | ||||||
|     USBD, |     USBD, | ||||||
|     UARTE1, |     UARTE1, | ||||||
| @ -374,5 +375,4 @@ embassy_hal_internal::interrupt_mod!( | |||||||
|     CRYPTOCELL, |     CRYPTOCELL, | ||||||
|     PWM3, |     PWM3, | ||||||
|     SPIM3, |     SPIM3, | ||||||
|     I2S, |  | ||||||
| ); | ); | ||||||
|  | |||||||
| @ -2,71 +2,9 @@ | |||||||
| #[allow(unused_imports)] | #[allow(unused_imports)] | ||||||
| #[rustfmt::skip] | #[rustfmt::skip] | ||||||
| pub mod pac { | pub mod pac { | ||||||
|     // The nRF5340 has a secure and non-secure (NS) mode.
 |     pub use nrf_pac::*; | ||||||
|     // To avoid cfg spam, we remove _ns or _s suffixes here.
 |  | ||||||
| 
 | 
 | ||||||
|     #[cfg(feature="rt")] |     #[cfg(feature = "_ns")] | ||||||
|     pub use nrf_pac::NVIC_PRIO_BITS; |  | ||||||
|     pub use nrf_pac::{common, shared}; |  | ||||||
| 
 |  | ||||||
|     #[cfg(feature="rt")] |  | ||||||
|     #[doc(no_inline)] |  | ||||||
|     pub use nrf_pac::interrupt; |  | ||||||
| 
 |  | ||||||
|     #[doc(no_inline)] |  | ||||||
|     pub use nrf_pac::{ |  | ||||||
|         Interrupt, |  | ||||||
| 
 |  | ||||||
|         cache_s as cache, |  | ||||||
|         cachedata_s as cachedata, |  | ||||||
|         cacheinfo_s as cacheinfo, |  | ||||||
|         clock_ns as clock, |  | ||||||
|         comp_ns as comp, |  | ||||||
|         cryptocell_s as cryptocell, |  | ||||||
|         cti_s as cti, |  | ||||||
|         ctrlap_ns as ctrlap, |  | ||||||
|         dcnf_ns as dcnf, |  | ||||||
|         dppic_ns as dppic, |  | ||||||
|         egu_ns as egu, |  | ||||||
|         ficr_s as ficr, |  | ||||||
|         fpu_ns as fpu, |  | ||||||
|         gpiote_s as gpiote, |  | ||||||
|         i2s_ns as i2s, |  | ||||||
|         ipc_ns as ipc, |  | ||||||
|         kmu_ns as kmu, |  | ||||||
|         lpcomp_ns as lpcomp, |  | ||||||
|         mutex_ns as mutex, |  | ||||||
|         nfct_ns as nfct, |  | ||||||
|         nvmc_ns as nvmc, |  | ||||||
|         oscillators_ns as oscillators, |  | ||||||
|         gpio_ns as gpio, |  | ||||||
|         pdm_ns as pdm, |  | ||||||
|         power_ns as power, |  | ||||||
|         pwm_ns as pwm, |  | ||||||
|         qdec_ns as qdec, |  | ||||||
|         qspi_ns as qspi, |  | ||||||
|         regulators_ns as regulators, |  | ||||||
|         reset_ns as reset, |  | ||||||
|         rtc_ns as rtc, |  | ||||||
|         saadc_ns as saadc, |  | ||||||
|         spim_ns as spim, |  | ||||||
|         spis_ns as spis, |  | ||||||
|         spu_s as spu, |  | ||||||
|         tad_s as tad, |  | ||||||
|         timer_ns as timer, |  | ||||||
|         twim_ns as twim, |  | ||||||
|         twis_ns as twis, |  | ||||||
|         uarte_ns as uarte, |  | ||||||
|         uicr_s as uicr, |  | ||||||
|         usbd_ns as usbd, |  | ||||||
|         usbregulator_ns as usbregulator, |  | ||||||
|         vmc_ns as vmc, |  | ||||||
|         wdt_ns as wdt, |  | ||||||
|     }; |  | ||||||
|     
 |  | ||||||
|     /// Non-Secure mode (NS) peripherals
 |  | ||||||
|     pub mod ns { |  | ||||||
|         #[cfg(feature = "nrf5340-app-ns")] |  | ||||||
|     #[doc(no_inline)] |     #[doc(no_inline)] | ||||||
|     pub use nrf_pac::{ |     pub use nrf_pac::{ | ||||||
|         CLOCK_NS as CLOCK, |         CLOCK_NS as CLOCK, | ||||||
| @ -136,11 +74,8 @@ pub mod pac { | |||||||
|         WDT0_NS as WDT0, |         WDT0_NS as WDT0, | ||||||
|         WDT1_NS as WDT1, |         WDT1_NS as WDT1, | ||||||
|     }; |     }; | ||||||
|     } |  | ||||||
| 
 | 
 | ||||||
|     /// Secure mode (S) peripherals
 |     #[cfg(feature = "_s")] | ||||||
|     pub mod s { |  | ||||||
|         #[cfg(feature = "nrf5340-app-s")] |  | ||||||
|     #[doc(no_inline)] |     #[doc(no_inline)] | ||||||
|     pub use nrf_pac::{ |     pub use nrf_pac::{ | ||||||
|         CACHEDATA_S as CACHEDATA, |         CACHEDATA_S as CACHEDATA, | ||||||
| @ -219,12 +154,6 @@ pub mod pac { | |||||||
|         WDT0_S as WDT0, |         WDT0_S as WDT0, | ||||||
|         WDT1_S as WDT1, |         WDT1_S as WDT1, | ||||||
|     }; |     }; | ||||||
|     } |  | ||||||
| 
 |  | ||||||
|     #[cfg(feature = "_ns")] |  | ||||||
|     pub use ns::*; |  | ||||||
|     #[cfg(feature = "_s")] |  | ||||||
|     pub use s::*; |  | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
| /// The maximum buffer size that the EasyDMA can send/recv in one operation.
 | /// The maximum buffer size that the EasyDMA can send/recv in one operation.
 | ||||||
|  | |||||||
| @ -2,55 +2,10 @@ | |||||||
| #[allow(unused_imports)] | #[allow(unused_imports)] | ||||||
| #[rustfmt::skip] | #[rustfmt::skip] | ||||||
| pub mod pac { | pub mod pac { | ||||||
|     // The nRF5340 has a secure and non-secure (NS) mode.
 |     pub use nrf_pac::*; | ||||||
|     // To avoid cfg spam, we remove _ns or _s suffixes here.
 |  | ||||||
| 
 |  | ||||||
|     #[cfg(feature="rt")] |  | ||||||
|     pub use nrf_pac::NVIC_PRIO_BITS; |  | ||||||
|     pub use nrf_pac::{common, shared}; |  | ||||||
| 
 |  | ||||||
|     #[cfg(feature="rt")] |  | ||||||
|     #[doc(no_inline)] |  | ||||||
|     pub use nrf_pac::interrupt; |  | ||||||
| 
 | 
 | ||||||
|     #[doc(no_inline)] |     #[doc(no_inline)] | ||||||
|     pub use nrf_pac::{ |     pub use nrf_pac::{ | ||||||
|         Interrupt, |  | ||||||
| 
 |  | ||||||
|         aar_ns as aar, |  | ||||||
|         acl_ns as acl, |  | ||||||
|         appmutex_ns as appmutex, |  | ||||||
|         ccm_ns as ccm, |  | ||||||
|         clock_ns as clock, |  | ||||||
|         cti_ns as cti, |  | ||||||
|         ctrlap_ns as ctrlap, |  | ||||||
|         dcnf_ns as dcnf, |  | ||||||
|         dppic_ns as dppic, |  | ||||||
|         ecb_ns as ecb, |  | ||||||
|         egu_ns as egu, |  | ||||||
|         ficr_ns as ficr, |  | ||||||
|         gpiote_ns as gpiote, |  | ||||||
|         ipc_ns as ipc, |  | ||||||
|         nvmc_ns as nvmc, |  | ||||||
|         gpio_ns as gpio, |  | ||||||
|         power_ns as power, |  | ||||||
|         radio_ns as radio, |  | ||||||
|         reset_ns as reset, |  | ||||||
|         rng_ns as rng, |  | ||||||
|         rtc_ns as rtc, |  | ||||||
|         spim_ns as spim, |  | ||||||
|         spis_ns as spis, |  | ||||||
|         swi_ns as swi, |  | ||||||
|         temp_ns as temp, |  | ||||||
|         timer_ns as timer, |  | ||||||
|         twim_ns as twim, |  | ||||||
|         twis_ns as twis, |  | ||||||
|         uarte_ns as uarte, |  | ||||||
|         uicr_ns as uicr, |  | ||||||
|         vmc_ns as vmc, |  | ||||||
|         vreqctrl_ns as vreqctrl, |  | ||||||
|         wdt_ns as wdt, |  | ||||||
| 
 |  | ||||||
|         AAR_NS as AAR, |         AAR_NS as AAR, | ||||||
|         ACL_NS as ACL, |         ACL_NS as ACL, | ||||||
|         APPMUTEX_NS as APPMUTEX, |         APPMUTEX_NS as APPMUTEX, | ||||||
| @ -93,7 +48,6 @@ pub mod pac { | |||||||
|         VREQCTRL_NS as VREQCTRL, |         VREQCTRL_NS as VREQCTRL, | ||||||
|         WDT_NS as WDT, |         WDT_NS as WDT, | ||||||
|     }; |     }; | ||||||
|     
 |  | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
| /// The maximum buffer size that the EasyDMA can send/recv in one operation.
 | /// The maximum buffer size that the EasyDMA can send/recv in one operation.
 | ||||||
|  | |||||||
| @ -2,56 +2,9 @@ | |||||||
| #[allow(unused_imports)] | #[allow(unused_imports)] | ||||||
| #[rustfmt::skip] | #[rustfmt::skip] | ||||||
| pub mod pac { | pub mod pac { | ||||||
|     // The nRF9120 has a secure and non-secure (NS) mode.
 |     pub use nrf_pac::*; | ||||||
|     // To avoid cfg spam, we remove _ns or _s suffixes here.
 |  | ||||||
| 
 | 
 | ||||||
|     #[cfg(feature="rt")] |     #[cfg(feature = "_ns")] | ||||||
|     pub use nrf_pac::NVIC_PRIO_BITS; |  | ||||||
|     pub use nrf_pac::{common, shared}; |  | ||||||
| 
 |  | ||||||
|     #[cfg(feature="rt")] |  | ||||||
|     #[doc(no_inline)] |  | ||||||
|     pub use nrf_pac::interrupt; |  | ||||||
| 
 |  | ||||||
|     #[doc(no_inline)] |  | ||||||
|     pub use nrf_pac::{ |  | ||||||
|         Interrupt, |  | ||||||
| 
 |  | ||||||
|         cc_host_rgf_s as cc_host_rgf, |  | ||||||
|         clock_ns as clock, |  | ||||||
|         cryptocell_s as cryptocell, |  | ||||||
|         ctrl_ap_peri_s as ctrl_ap_peri, |  | ||||||
|         dppic_ns as dppic, |  | ||||||
|         egu_ns as egu, |  | ||||||
|         ficr_s as ficr, |  | ||||||
|         fpu_ns as fpu, |  | ||||||
|         gpiote_s as gpiote, |  | ||||||
|         i2s_ns as i2s, |  | ||||||
|         ipc_ns as ipc, |  | ||||||
|         kmu_ns as kmu, |  | ||||||
|         nvmc_ns as nvmc, |  | ||||||
|         gpio_ns as gpio, |  | ||||||
|         pdm_ns as pdm, |  | ||||||
|         power_ns as power, |  | ||||||
|         pwm_ns as pwm, |  | ||||||
|         regulators_ns as regulators, |  | ||||||
|         rtc_ns as rtc, |  | ||||||
|         saadc_ns as saadc, |  | ||||||
|         spim_ns as spim, |  | ||||||
|         spis_ns as spis, |  | ||||||
|         spu_s as spu, |  | ||||||
|         tad_s as tad, |  | ||||||
|         timer_ns as timer, |  | ||||||
|         twim_ns as twim, |  | ||||||
|         twis_ns as twis, |  | ||||||
|         uarte_ns as uarte, |  | ||||||
|         uicr_s as uicr, |  | ||||||
|         vmc_ns as vmc, |  | ||||||
|         wdt_ns as wdt, |  | ||||||
|     }; |  | ||||||
|     
 |  | ||||||
|     /// Non-Secure mode (NS) peripherals
 |  | ||||||
|     pub mod ns { |  | ||||||
|     #[doc(no_inline)] |     #[doc(no_inline)] | ||||||
|     pub use nrf_pac::{ |     pub use nrf_pac::{ | ||||||
|         CLOCK_NS as CLOCK, |         CLOCK_NS as CLOCK, | ||||||
| @ -105,10 +58,8 @@ pub mod pac { | |||||||
|         VMC_NS as VMC, |         VMC_NS as VMC, | ||||||
|         WDT_NS as WDT, |         WDT_NS as WDT, | ||||||
|     }; |     }; | ||||||
|     } |  | ||||||
| 
 | 
 | ||||||
|     /// Secure mode (S) peripherals
 |     #[cfg(feature = "_s")] | ||||||
|     pub mod s { |  | ||||||
|     #[doc(no_inline)] |     #[doc(no_inline)] | ||||||
|     pub use nrf_pac::{ |     pub use nrf_pac::{ | ||||||
|         CC_HOST_RGF_S as CC_HOST_RGF, |         CC_HOST_RGF_S as CC_HOST_RGF, | ||||||
| @ -169,12 +120,6 @@ pub mod pac { | |||||||
|         VMC_S as VMC, |         VMC_S as VMC, | ||||||
|         WDT_S as WDT, |         WDT_S as WDT, | ||||||
|     }; |     }; | ||||||
|     } |  | ||||||
| 
 |  | ||||||
|     #[cfg(feature = "_ns")] |  | ||||||
|     pub use ns::*; |  | ||||||
|     #[cfg(feature = "_s")] |  | ||||||
|     pub use s::*; |  | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
| /// The maximum buffer size that the EasyDMA can send/recv in one operation.
 | /// The maximum buffer size that the EasyDMA can send/recv in one operation.
 | ||||||
| @ -295,30 +240,30 @@ embassy_hal_internal::peripherals! { | |||||||
|     EGU5, |     EGU5, | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
| impl_uarte!(SERIAL0, UARTE0, SPIM0_SPIS0_TWIM0_TWIS0_UARTE0); | impl_uarte!(SERIAL0, UARTE0, SERIAL0); | ||||||
| impl_uarte!(SERIAL1, UARTE1, SPIM1_SPIS1_TWIM1_TWIS1_UARTE1); | impl_uarte!(SERIAL1, UARTE1, SERIAL1); | ||||||
| impl_uarte!(SERIAL2, UARTE2, SPIM2_SPIS2_TWIM2_TWIS2_UARTE2); | impl_uarte!(SERIAL2, UARTE2, SERIAL2); | ||||||
| impl_uarte!(SERIAL3, UARTE3, SPIM3_SPIS3_TWIM3_TWIS3_UARTE3); | impl_uarte!(SERIAL3, UARTE3, SERIAL3); | ||||||
| 
 | 
 | ||||||
| impl_spim!(SERIAL0, SPIM0, SPIM0_SPIS0_TWIM0_TWIS0_UARTE0); | impl_spim!(SERIAL0, SPIM0, SERIAL0); | ||||||
| impl_spim!(SERIAL1, SPIM1, SPIM1_SPIS1_TWIM1_TWIS1_UARTE1); | impl_spim!(SERIAL1, SPIM1, SERIAL1); | ||||||
| impl_spim!(SERIAL2, SPIM2, SPIM2_SPIS2_TWIM2_TWIS2_UARTE2); | impl_spim!(SERIAL2, SPIM2, SERIAL2); | ||||||
| impl_spim!(SERIAL3, SPIM3, SPIM3_SPIS3_TWIM3_TWIS3_UARTE3); | impl_spim!(SERIAL3, SPIM3, SERIAL3); | ||||||
| 
 | 
 | ||||||
| impl_spis!(SERIAL0, SPIS0, SPIM0_SPIS0_TWIM0_TWIS0_UARTE0); | impl_spis!(SERIAL0, SPIS0, SERIAL0); | ||||||
| impl_spis!(SERIAL1, SPIS1, SPIM1_SPIS1_TWIM1_TWIS1_UARTE1); | impl_spis!(SERIAL1, SPIS1, SERIAL1); | ||||||
| impl_spis!(SERIAL2, SPIS2, SPIM2_SPIS2_TWIM2_TWIS2_UARTE2); | impl_spis!(SERIAL2, SPIS2, SERIAL2); | ||||||
| impl_spis!(SERIAL3, SPIS3, SPIM3_SPIS3_TWIM3_TWIS3_UARTE3); | impl_spis!(SERIAL3, SPIS3, SERIAL3); | ||||||
| 
 | 
 | ||||||
| impl_twim!(SERIAL0, TWIM0, SPIM0_SPIS0_TWIM0_TWIS0_UARTE0); | impl_twim!(SERIAL0, TWIM0, SERIAL0); | ||||||
| impl_twim!(SERIAL1, TWIM1, SPIM1_SPIS1_TWIM1_TWIS1_UARTE1); | impl_twim!(SERIAL1, TWIM1, SERIAL1); | ||||||
| impl_twim!(SERIAL2, TWIM2, SPIM2_SPIS2_TWIM2_TWIS2_UARTE2); | impl_twim!(SERIAL2, TWIM2, SERIAL2); | ||||||
| impl_twim!(SERIAL3, TWIM3, SPIM3_SPIS3_TWIM3_TWIS3_UARTE3); | impl_twim!(SERIAL3, TWIM3, SERIAL3); | ||||||
| 
 | 
 | ||||||
| impl_twis!(SERIAL0, TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_UARTE0); | impl_twis!(SERIAL0, TWIS0, SERIAL0); | ||||||
| impl_twis!(SERIAL1, TWIS1, SPIM1_SPIS1_TWIM1_TWIS1_UARTE1); | impl_twis!(SERIAL1, TWIS1, SERIAL1); | ||||||
| impl_twis!(SERIAL2, TWIS2, SPIM2_SPIS2_TWIM2_TWIS2_UARTE2); | impl_twis!(SERIAL2, TWIS2, SERIAL2); | ||||||
| impl_twis!(SERIAL3, TWIS3, SPIM3_SPIS3_TWIM3_TWIS3_UARTE3); | impl_twis!(SERIAL3, TWIS3, SERIAL3); | ||||||
| 
 | 
 | ||||||
| impl_pwm!(PWM0, PWM0, PWM0); | impl_pwm!(PWM0, PWM0, PWM0); | ||||||
| impl_pwm!(PWM1, PWM1, PWM1); | impl_pwm!(PWM1, PWM1, PWM1); | ||||||
| @ -400,10 +345,10 @@ impl_egu!(EGU5, EGU5, EGU5); | |||||||
| embassy_hal_internal::interrupt_mod!( | embassy_hal_internal::interrupt_mod!( | ||||||
|     SPU, |     SPU, | ||||||
|     CLOCK_POWER, |     CLOCK_POWER, | ||||||
|     SPIM0_SPIS0_TWIM0_TWIS0_UARTE0, |     SERIAL0, | ||||||
|     SPIM1_SPIS1_TWIM1_TWIS1_UARTE1, |     SERIAL1, | ||||||
|     SPIM2_SPIS2_TWIM2_TWIS2_UARTE2, |     SERIAL2, | ||||||
|     SPIM3_SPIS3_TWIM3_TWIS3_UARTE3, |     SERIAL3, | ||||||
|     GPIOTE0, |     GPIOTE0, | ||||||
|     SAADC, |     SAADC, | ||||||
|     TIMER0, |     TIMER0, | ||||||
| @ -421,8 +366,8 @@ embassy_hal_internal::interrupt_mod!( | |||||||
|     PWM0, |     PWM0, | ||||||
|     PWM1, |     PWM1, | ||||||
|     PWM2, |     PWM2, | ||||||
|     PDM, |  | ||||||
|     PWM3, |     PWM3, | ||||||
|  |     PDM, | ||||||
|     I2S, |     I2S, | ||||||
|     IPC, |     IPC, | ||||||
|     FPU, |     FPU, | ||||||
|  | |||||||
| @ -2,56 +2,9 @@ | |||||||
| #[allow(unused_imports)] | #[allow(unused_imports)] | ||||||
| #[rustfmt::skip] | #[rustfmt::skip] | ||||||
| pub mod pac { | pub mod pac { | ||||||
|     // The nRF9160 has a secure and non-secure (NS) mode.
 |     pub use nrf_pac::*; | ||||||
|     // To avoid cfg spam, we remove _ns or _s suffixes here.
 |  | ||||||
| 
 | 
 | ||||||
|     #[cfg(feature="rt")] |     #[cfg(feature = "_ns")] | ||||||
|     pub use nrf_pac::NVIC_PRIO_BITS; |  | ||||||
|     pub use nrf_pac::{common, shared}; |  | ||||||
| 
 |  | ||||||
|     #[cfg(feature="rt")] |  | ||||||
|     #[doc(no_inline)] |  | ||||||
|     pub use nrf_pac::interrupt; |  | ||||||
| 
 |  | ||||||
|     #[doc(no_inline)] |  | ||||||
|     pub use nrf_pac::{ |  | ||||||
|         Interrupt, |  | ||||||
| 
 |  | ||||||
|         cc_host_rgf_s as cc_host_rgf, |  | ||||||
|         clock_ns as clock, |  | ||||||
|         cryptocell_s as cryptocell, |  | ||||||
|         ctrl_ap_peri_s as ctrl_ap_peri, |  | ||||||
|         dppic_ns as dppic, |  | ||||||
|         egu_ns as egu, |  | ||||||
|         ficr_s as ficr, |  | ||||||
|         fpu_ns as fpu, |  | ||||||
|         gpiote_s as gpiote, |  | ||||||
|         i2s_ns as i2s, |  | ||||||
|         ipc_ns as ipc, |  | ||||||
|         kmu_ns as kmu, |  | ||||||
|         nvmc_ns as nvmc, |  | ||||||
|         gpio_ns as gpio, |  | ||||||
|         pdm_ns as pdm, |  | ||||||
|         power_ns as power, |  | ||||||
|         pwm_ns as pwm, |  | ||||||
|         regulators_ns as regulators, |  | ||||||
|         rtc_ns as rtc, |  | ||||||
|         saadc_ns as saadc, |  | ||||||
|         spim_ns as spim, |  | ||||||
|         spis_ns as spis, |  | ||||||
|         spu_s as spu, |  | ||||||
|         tad_s as tad, |  | ||||||
|         timer_ns as timer, |  | ||||||
|         twim_ns as twim, |  | ||||||
|         twis_ns as twis, |  | ||||||
|         uarte_ns as uarte, |  | ||||||
|         uicr_s as uicr, |  | ||||||
|         vmc_ns as vmc, |  | ||||||
|         wdt_ns as wdt, |  | ||||||
|     }; |  | ||||||
|     
 |  | ||||||
|     /// Non-Secure mode (NS) peripherals
 |  | ||||||
|     pub mod ns { |  | ||||||
|     #[doc(no_inline)] |     #[doc(no_inline)] | ||||||
|     pub use nrf_pac::{ |     pub use nrf_pac::{ | ||||||
|         CLOCK_NS as CLOCK, |         CLOCK_NS as CLOCK, | ||||||
| @ -105,10 +58,8 @@ pub mod pac { | |||||||
|         VMC_NS as VMC, |         VMC_NS as VMC, | ||||||
|         WDT_NS as WDT, |         WDT_NS as WDT, | ||||||
|     }; |     }; | ||||||
|     } |  | ||||||
| 
 | 
 | ||||||
|     /// Secure mode (S) peripherals
 |     #[cfg(feature = "_s")] | ||||||
|     pub mod s { |  | ||||||
|     #[doc(no_inline)] |     #[doc(no_inline)] | ||||||
|     pub use nrf_pac::{ |     pub use nrf_pac::{ | ||||||
|         CC_HOST_RGF_S as CC_HOST_RGF, |         CC_HOST_RGF_S as CC_HOST_RGF, | ||||||
| @ -169,12 +120,6 @@ pub mod pac { | |||||||
|         VMC_S as VMC, |         VMC_S as VMC, | ||||||
|         WDT_S as WDT, |         WDT_S as WDT, | ||||||
|     }; |     }; | ||||||
|     } |  | ||||||
| 
 |  | ||||||
|     #[cfg(feature = "_ns")] |  | ||||||
|     pub use ns::*; |  | ||||||
|     #[cfg(feature = "_s")] |  | ||||||
|     pub use s::*; |  | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
| /// The maximum buffer size that the EasyDMA can send/recv in one operation.
 | /// The maximum buffer size that the EasyDMA can send/recv in one operation.
 | ||||||
| @ -295,30 +240,30 @@ embassy_hal_internal::peripherals! { | |||||||
|     EGU5, |     EGU5, | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
| impl_uarte!(SERIAL0, UARTE0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0); | impl_uarte!(SERIAL0, UARTE0, SERIAL0); | ||||||
| impl_uarte!(SERIAL1, UARTE1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1); | impl_uarte!(SERIAL1, UARTE1, SERIAL1); | ||||||
| impl_uarte!(SERIAL2, UARTE2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2); | impl_uarte!(SERIAL2, UARTE2, SERIAL2); | ||||||
| impl_uarte!(SERIAL3, UARTE3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3); | impl_uarte!(SERIAL3, UARTE3, SERIAL3); | ||||||
| 
 | 
 | ||||||
| impl_spim!(SERIAL0, SPIM0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0); | impl_spim!(SERIAL0, SPIM0, SERIAL0); | ||||||
| impl_spim!(SERIAL1, SPIM1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1); | impl_spim!(SERIAL1, SPIM1, SERIAL1); | ||||||
| impl_spim!(SERIAL2, SPIM2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2); | impl_spim!(SERIAL2, SPIM2, SERIAL2); | ||||||
| impl_spim!(SERIAL3, SPIM3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3); | impl_spim!(SERIAL3, SPIM3, SERIAL3); | ||||||
| 
 | 
 | ||||||
| impl_spis!(SERIAL0, SPIS0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0); | impl_spis!(SERIAL0, SPIS0, SERIAL0); | ||||||
| impl_spis!(SERIAL1, SPIS1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1); | impl_spis!(SERIAL1, SPIS1, SERIAL1); | ||||||
| impl_spis!(SERIAL2, SPIS2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2); | impl_spis!(SERIAL2, SPIS2, SERIAL2); | ||||||
| impl_spis!(SERIAL3, SPIS3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3); | impl_spis!(SERIAL3, SPIS3, SERIAL3); | ||||||
| 
 | 
 | ||||||
| impl_twim!(SERIAL0, TWIM0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0); | impl_twim!(SERIAL0, TWIM0, SERIAL0); | ||||||
| impl_twim!(SERIAL1, TWIM1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1); | impl_twim!(SERIAL1, TWIM1, SERIAL1); | ||||||
| impl_twim!(SERIAL2, TWIM2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2); | impl_twim!(SERIAL2, TWIM2, SERIAL2); | ||||||
| impl_twim!(SERIAL3, TWIM3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3); | impl_twim!(SERIAL3, TWIM3, SERIAL3); | ||||||
| 
 | 
 | ||||||
| impl_twis!(SERIAL0, TWIS0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0); | impl_twis!(SERIAL0, TWIS0, SERIAL0); | ||||||
| impl_twis!(SERIAL1, TWIS1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1); | impl_twis!(SERIAL1, TWIS1, SERIAL1); | ||||||
| impl_twis!(SERIAL2, TWIS2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2); | impl_twis!(SERIAL2, TWIS2, SERIAL2); | ||||||
| impl_twis!(SERIAL3, TWIS3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3); | impl_twis!(SERIAL3, TWIS3, SERIAL3); | ||||||
| 
 | 
 | ||||||
| impl_pwm!(PWM0, PWM0, PWM0); | impl_pwm!(PWM0, PWM0, PWM0); | ||||||
| impl_pwm!(PWM1, PWM1, PWM1); | impl_pwm!(PWM1, PWM1, PWM1); | ||||||
| @ -400,10 +345,10 @@ impl_egu!(EGU5, EGU5, EGU5); | |||||||
| embassy_hal_internal::interrupt_mod!( | embassy_hal_internal::interrupt_mod!( | ||||||
|     SPU, |     SPU, | ||||||
|     CLOCK_POWER, |     CLOCK_POWER, | ||||||
|     UARTE0_SPIM0_SPIS0_TWIM0_TWIS0, |     SERIAL0, | ||||||
|     UARTE1_SPIM1_SPIS1_TWIM1_TWIS1, |     SERIAL1, | ||||||
|     UARTE2_SPIM2_SPIS2_TWIM2_TWIS2, |     SERIAL2, | ||||||
|     UARTE3_SPIM3_SPIS3_TWIM3_TWIS3, |     SERIAL3, | ||||||
|     GPIOTE0, |     GPIOTE0, | ||||||
|     SAADC, |     SAADC, | ||||||
|     TIMER0, |     TIMER0, | ||||||
| @ -421,8 +366,8 @@ embassy_hal_internal::interrupt_mod!( | |||||||
|     PWM0, |     PWM0, | ||||||
|     PWM1, |     PWM1, | ||||||
|     PWM2, |     PWM2, | ||||||
|     PDM, |  | ||||||
|     PWM3, |     PWM3, | ||||||
|  |     PDM, | ||||||
|     I2S, |     I2S, | ||||||
|     IPC, |     IPC, | ||||||
|     FPU, |     FPU, | ||||||
|  | |||||||
| @ -170,7 +170,7 @@ mod chip; | |||||||
| ///
 | ///
 | ||||||
| /// bind_interrupts!(struct Irqs {
 | /// bind_interrupts!(struct Irqs {
 | ||||||
| ///     SPIM3 => spim::InterruptHandler<peripherals::SPI3>;
 | ///     SPIM3 => spim::InterruptHandler<peripherals::SPI3>;
 | ||||||
| ///     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 => twim::InterruptHandler<peripherals::TWISPI0>;
 | ///     TWISPI0 => twim::InterruptHandler<peripherals::TWISPI0>;
 | ||||||
| /// });
 | /// });
 | ||||||
| /// ```
 | /// ```
 | ||||||
| 
 | 
 | ||||||
|  | |||||||
| @ -132,7 +132,7 @@ impl RtcDriver { | |||||||
| 
 | 
 | ||||||
|         r.intenset().write(|w| { |         r.intenset().write(|w| { | ||||||
|             w.set_ovrflw(true); |             w.set_ovrflw(true); | ||||||
|             w.set_compare3(true); |             w.set_compare(3, true); | ||||||
|         }); |         }); | ||||||
| 
 | 
 | ||||||
|         r.tasks_clear().write_value(1); |         r.tasks_clear().write_value(1); | ||||||
|  | |||||||
| @ -29,14 +29,14 @@ pub trait VbusDetect { | |||||||
| } | } | ||||||
| 
 | 
 | ||||||
| #[cfg(not(feature = "_nrf5340"))] | #[cfg(not(feature = "_nrf5340"))] | ||||||
| type UsbRegIrq = interrupt::typelevel::POWER_CLOCK; | type UsbRegIrq = interrupt::typelevel::CLOCK_POWER; | ||||||
| #[cfg(feature = "_nrf5340")] | #[cfg(feature = "_nrf5340")] | ||||||
| type UsbRegIrq = interrupt::typelevel::USBREGULATOR; | type UsbRegIrq = interrupt::typelevel::USBREGULATOR; | ||||||
| 
 | 
 | ||||||
| #[cfg(not(feature = "_nrf5340"))] | #[cfg(not(feature = "_nrf5340"))] | ||||||
| const USB_REG_PERI: pac::power::Power = pac::POWER; | const USB_REG_PERI: pac::power::Power = pac::POWER; | ||||||
| #[cfg(feature = "_nrf5340")] | #[cfg(feature = "_nrf5340")] | ||||||
| const USB_REG_PERI: pac::usbregulator::Usbregulator = pac::USBREGULATOR; | const USB_REG_PERI: pac::usbreg::Usbreg = pac::USBREGULATOR; | ||||||
| 
 | 
 | ||||||
| /// Interrupt handler.
 | /// Interrupt handler.
 | ||||||
| pub struct InterruptHandler { | pub struct InterruptHandler { | ||||||
|  | |||||||
| @ -4,7 +4,7 @@ | |||||||
| 
 | 
 | ||||||
| use {defmt_rtt as _, panic_probe as _}; | use {defmt_rtt as _, panic_probe as _}; | ||||||
| 
 | 
 | ||||||
| #[rtic::app(device = embassy_nrf, peripherals = false, dispatchers = [SWI0_EGU0, SWI1_EGU1])] | #[rtic::app(device = embassy_nrf, peripherals = false, dispatchers = [EGU0_SWI0, EGU1_SWI1])] | ||||||
| mod app { | mod app { | ||||||
|     use defmt::info; |     use defmt::info; | ||||||
|     use embassy_nrf::gpio::{Level, Output, OutputDrive}; |     use embassy_nrf::gpio::{Level, Output, OutputDrive}; | ||||||
|  | |||||||
| @ -9,7 +9,7 @@ use embedded_io_async::Write; | |||||||
| use {defmt_rtt as _, panic_probe as _}; | use {defmt_rtt as _, panic_probe as _}; | ||||||
| 
 | 
 | ||||||
| bind_interrupts!(struct Irqs { | bind_interrupts!(struct Irqs { | ||||||
|     UARTE0_UART0 => buffered_uarte::InterruptHandler<peripherals::UARTE0>; |     UARTE0 => buffered_uarte::InterruptHandler<peripherals::UARTE0>; | ||||||
| }); | }); | ||||||
| 
 | 
 | ||||||
| #[embassy_executor::main] | #[embassy_executor::main] | ||||||
|  | |||||||
| @ -112,12 +112,12 @@ static EXECUTOR_MED: InterruptExecutor = InterruptExecutor::new(); | |||||||
| static EXECUTOR_LOW: StaticCell<Executor> = StaticCell::new(); | static EXECUTOR_LOW: StaticCell<Executor> = StaticCell::new(); | ||||||
| 
 | 
 | ||||||
| #[interrupt] | #[interrupt] | ||||||
| unsafe fn SWI1_EGU1() { | unsafe fn EGU1_SWI1() { | ||||||
|     EXECUTOR_HIGH.on_interrupt() |     EXECUTOR_HIGH.on_interrupt() | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
| #[interrupt] | #[interrupt] | ||||||
| unsafe fn SWI0_EGU0() { | unsafe fn EGU0_SWI0() { | ||||||
|     EXECUTOR_MED.on_interrupt() |     EXECUTOR_MED.on_interrupt() | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
| @ -127,14 +127,14 @@ fn main() -> ! { | |||||||
| 
 | 
 | ||||||
|     let _p = embassy_nrf::init(Default::default()); |     let _p = embassy_nrf::init(Default::default()); | ||||||
| 
 | 
 | ||||||
|     // High-priority executor: SWI1_EGU1, priority level 6
 |     // High-priority executor: EGU1_SWI1, priority level 6
 | ||||||
|     interrupt::SWI1_EGU1.set_priority(Priority::P6); |     interrupt::EGU1_SWI1.set_priority(Priority::P6); | ||||||
|     let spawner = EXECUTOR_HIGH.start(interrupt::SWI1_EGU1); |     let spawner = EXECUTOR_HIGH.start(interrupt::EGU1_SWI1); | ||||||
|     unwrap!(spawner.spawn(run_high())); |     unwrap!(spawner.spawn(run_high())); | ||||||
| 
 | 
 | ||||||
|     // Medium-priority executor: SWI0_EGU0, priority level 7
 |     // Medium-priority executor: EGU0_SWI0, priority level 7
 | ||||||
|     interrupt::SWI0_EGU0.set_priority(Priority::P7); |     interrupt::EGU0_SWI0.set_priority(Priority::P7); | ||||||
|     let spawner = EXECUTOR_MED.start(interrupt::SWI0_EGU0); |     let spawner = EXECUTOR_MED.start(interrupt::EGU0_SWI0); | ||||||
|     unwrap!(spawner.spawn(run_med())); |     unwrap!(spawner.spawn(run_med())); | ||||||
| 
 | 
 | ||||||
|     // Low priority executor: runs in thread mode, using WFE/SEV
 |     // Low priority executor: runs in thread mode, using WFE/SEV
 | ||||||
|  | |||||||
| @ -8,7 +8,7 @@ use embassy_nrf::{bind_interrupts, peripherals, spis}; | |||||||
| use {defmt_rtt as _, panic_probe as _}; | use {defmt_rtt as _, panic_probe as _}; | ||||||
| 
 | 
 | ||||||
| bind_interrupts!(struct Irqs { | bind_interrupts!(struct Irqs { | ||||||
|     SPIM2_SPIS2_SPI2 => spis::InterruptHandler<peripherals::SPI2>; |     SPI2 => spis::InterruptHandler<peripherals::SPI2>; | ||||||
| }); | }); | ||||||
| 
 | 
 | ||||||
| #[embassy_executor::main] | #[embassy_executor::main] | ||||||
|  | |||||||
| @ -14,7 +14,7 @@ use {defmt_rtt as _, panic_probe as _}; | |||||||
| const ADDRESS: u8 = 0x50; | const ADDRESS: u8 = 0x50; | ||||||
| 
 | 
 | ||||||
| bind_interrupts!(struct Irqs { | bind_interrupts!(struct Irqs { | ||||||
|     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 => twim::InterruptHandler<peripherals::TWISPI0>; |     TWISPI0 => twim::InterruptHandler<peripherals::TWISPI0>; | ||||||
| }); | }); | ||||||
| 
 | 
 | ||||||
| #[embassy_executor::main] | #[embassy_executor::main] | ||||||
|  | |||||||
| @ -19,7 +19,7 @@ use {defmt_rtt as _, panic_probe as _}; | |||||||
| const ADDRESS: u8 = 0x50; | const ADDRESS: u8 = 0x50; | ||||||
| 
 | 
 | ||||||
| bind_interrupts!(struct Irqs { | bind_interrupts!(struct Irqs { | ||||||
|     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 => twim::InterruptHandler<peripherals::TWISPI0>; |     TWISPI0 => twim::InterruptHandler<peripherals::TWISPI0>; | ||||||
| }); | }); | ||||||
| 
 | 
 | ||||||
| #[embassy_executor::main] | #[embassy_executor::main] | ||||||
|  | |||||||
| @ -10,7 +10,7 @@ use embassy_nrf::{bind_interrupts, peripherals}; | |||||||
| use {defmt_rtt as _, panic_probe as _}; | use {defmt_rtt as _, panic_probe as _}; | ||||||
| 
 | 
 | ||||||
| bind_interrupts!(struct Irqs { | bind_interrupts!(struct Irqs { | ||||||
|     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 => twis::InterruptHandler<peripherals::TWISPI0>; |     TWISPI0 => twis::InterruptHandler<peripherals::TWISPI0>; | ||||||
| }); | }); | ||||||
| 
 | 
 | ||||||
| #[embassy_executor::main] | #[embassy_executor::main] | ||||||
|  | |||||||
| @ -7,7 +7,7 @@ use embassy_nrf::{bind_interrupts, peripherals, uarte}; | |||||||
| use {defmt_rtt as _, panic_probe as _}; | use {defmt_rtt as _, panic_probe as _}; | ||||||
| 
 | 
 | ||||||
| bind_interrupts!(struct Irqs { | bind_interrupts!(struct Irqs { | ||||||
|     UARTE0_UART0 => uarte::InterruptHandler<peripherals::UARTE0>; |     UARTE0 => uarte::InterruptHandler<peripherals::UARTE0>; | ||||||
| }); | }); | ||||||
| 
 | 
 | ||||||
| #[embassy_executor::main] | #[embassy_executor::main] | ||||||
|  | |||||||
| @ -8,7 +8,7 @@ use embassy_nrf::{bind_interrupts, uarte}; | |||||||
| use {defmt_rtt as _, panic_probe as _}; | use {defmt_rtt as _, panic_probe as _}; | ||||||
| 
 | 
 | ||||||
| bind_interrupts!(struct Irqs { | bind_interrupts!(struct Irqs { | ||||||
|     UARTE0_UART0 => uarte::InterruptHandler<UARTE0>; |     UARTE0 => uarte::InterruptHandler<UARTE0>; | ||||||
| }); | }); | ||||||
| 
 | 
 | ||||||
| #[embassy_executor::main] | #[embassy_executor::main] | ||||||
|  | |||||||
| @ -13,7 +13,7 @@ use {defmt_rtt as _, panic_probe as _}; | |||||||
| static CHANNEL: Channel<ThreadModeRawMutex, [u8; 8], 1> = Channel::new(); | static CHANNEL: Channel<ThreadModeRawMutex, [u8; 8], 1> = Channel::new(); | ||||||
| 
 | 
 | ||||||
| bind_interrupts!(struct Irqs { | bind_interrupts!(struct Irqs { | ||||||
|     UARTE0_UART0 => uarte::InterruptHandler<UARTE0>; |     UARTE0 => uarte::InterruptHandler<UARTE0>; | ||||||
| }); | }); | ||||||
| 
 | 
 | ||||||
| #[embassy_executor::main] | #[embassy_executor::main] | ||||||
|  | |||||||
| @ -18,7 +18,7 @@ use {defmt_rtt as _, panic_probe as _}; | |||||||
| 
 | 
 | ||||||
| bind_interrupts!(struct Irqs { | bind_interrupts!(struct Irqs { | ||||||
|     USBD => usb::InterruptHandler<peripherals::USBD>; |     USBD => usb::InterruptHandler<peripherals::USBD>; | ||||||
|     POWER_CLOCK => usb::vbus_detect::InterruptHandler; |     CLOCK_POWER => usb::vbus_detect::InterruptHandler; | ||||||
|     RNG => rng::InterruptHandler<peripherals::RNG>; |     RNG => rng::InterruptHandler<peripherals::RNG>; | ||||||
| }); | }); | ||||||
| 
 | 
 | ||||||
|  | |||||||
| @ -21,7 +21,7 @@ use {defmt_rtt as _, panic_probe as _}; | |||||||
| 
 | 
 | ||||||
| bind_interrupts!(struct Irqs { | bind_interrupts!(struct Irqs { | ||||||
|     USBD => usb::InterruptHandler<peripherals::USBD>; |     USBD => usb::InterruptHandler<peripherals::USBD>; | ||||||
|     POWER_CLOCK => usb::vbus_detect::InterruptHandler; |     CLOCK_POWER => usb::vbus_detect::InterruptHandler; | ||||||
| }); | }); | ||||||
| 
 | 
 | ||||||
| static SUSPENDED: AtomicBool = AtomicBool::new(false); | static SUSPENDED: AtomicBool = AtomicBool::new(false); | ||||||
|  | |||||||
| @ -16,7 +16,7 @@ use {defmt_rtt as _, panic_probe as _}; | |||||||
| 
 | 
 | ||||||
| bind_interrupts!(struct Irqs { | bind_interrupts!(struct Irqs { | ||||||
|     USBD => usb::InterruptHandler<peripherals::USBD>; |     USBD => usb::InterruptHandler<peripherals::USBD>; | ||||||
|     POWER_CLOCK => usb::vbus_detect::InterruptHandler; |     CLOCK_POWER => usb::vbus_detect::InterruptHandler; | ||||||
| }); | }); | ||||||
| 
 | 
 | ||||||
| #[embassy_executor::main] | #[embassy_executor::main] | ||||||
|  | |||||||
| @ -14,7 +14,7 @@ use {defmt_rtt as _, panic_probe as _}; | |||||||
| 
 | 
 | ||||||
| bind_interrupts!(struct Irqs { | bind_interrupts!(struct Irqs { | ||||||
|     USBD => usb::InterruptHandler<peripherals::USBD>; |     USBD => usb::InterruptHandler<peripherals::USBD>; | ||||||
|     POWER_CLOCK => usb::vbus_detect::InterruptHandler; |     CLOCK_POWER => usb::vbus_detect::InterruptHandler; | ||||||
| }); | }); | ||||||
| 
 | 
 | ||||||
| #[embassy_executor::main] | #[embassy_executor::main] | ||||||
|  | |||||||
| @ -14,7 +14,7 @@ use {defmt_rtt as _, panic_probe as _}; | |||||||
| 
 | 
 | ||||||
| bind_interrupts!(struct Irqs { | bind_interrupts!(struct Irqs { | ||||||
|     USBD => usb::InterruptHandler<peripherals::USBD>; |     USBD => usb::InterruptHandler<peripherals::USBD>; | ||||||
|     POWER_CLOCK => usb::vbus_detect::InterruptHandler; |     CLOCK_POWER => usb::vbus_detect::InterruptHandler; | ||||||
| }); | }); | ||||||
| 
 | 
 | ||||||
| type MyDriver = Driver<'static, peripherals::USBD, HardwareVbusDetect>; | type MyDriver = Driver<'static, peripherals::USBD, HardwareVbusDetect>; | ||||||
|  | |||||||
| @ -16,7 +16,7 @@ use {defmt_rtt as _, panic_probe as _}; | |||||||
| 
 | 
 | ||||||
| bind_interrupts!(struct Irqs { | bind_interrupts!(struct Irqs { | ||||||
|     USBD => usb::InterruptHandler<peripherals::USBD>; |     USBD => usb::InterruptHandler<peripherals::USBD>; | ||||||
|     POWER_CLOCK => usb::vbus_detect::InterruptHandler; |     CLOCK_POWER => usb::vbus_detect::InterruptHandler; | ||||||
| }); | }); | ||||||
| 
 | 
 | ||||||
| // This is a randomly generated GUID to allow clients on Windows to find our device
 | // This is a randomly generated GUID to allow clients on Windows to find our device
 | ||||||
|  | |||||||
| @ -7,7 +7,7 @@ use embassy_nrf::{bind_interrupts, peripherals, uarte}; | |||||||
| use {defmt_rtt as _, panic_probe as _}; | use {defmt_rtt as _, panic_probe as _}; | ||||||
| 
 | 
 | ||||||
| bind_interrupts!(struct Irqs { | bind_interrupts!(struct Irqs { | ||||||
|     SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 => uarte::InterruptHandler<peripherals::SERIAL0>; |     SERIAL0 => uarte::InterruptHandler<peripherals::SERIAL0>; | ||||||
| }); | }); | ||||||
| 
 | 
 | ||||||
| #[embassy_executor::main] | #[embassy_executor::main] | ||||||
|  | |||||||
| @ -28,7 +28,7 @@ fn IPC() { | |||||||
| } | } | ||||||
| 
 | 
 | ||||||
| bind_interrupts!(struct Irqs { | bind_interrupts!(struct Irqs { | ||||||
|     UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 => buffered_uarte::InterruptHandler<peripherals::SERIAL0>; |     SERIAL0 => buffered_uarte::InterruptHandler<peripherals::SERIAL0>; | ||||||
| }); | }); | ||||||
| 
 | 
 | ||||||
| #[embassy_executor::task] | #[embassy_executor::task] | ||||||
|  | |||||||
| @ -55,9 +55,9 @@ define_peris!( | |||||||
|     PIN_X = P0_13, |     PIN_X = P0_13, | ||||||
|     UART0 = UARTE0, |     UART0 = UARTE0, | ||||||
|     SPIM0 = TWISPI0, |     SPIM0 = TWISPI0, | ||||||
|     @irq UART0 = {UARTE0_UART0 => uarte::InterruptHandler<peripherals::UARTE0>;}, |     @irq UART0 = {UARTE0 => uarte::InterruptHandler<peripherals::UARTE0>;}, | ||||||
|     @irq UART0_BUFFERED = {UARTE0_UART0 => buffered_uarte::InterruptHandler<peripherals::UARTE0>;}, |     @irq UART0_BUFFERED = {UARTE0 => buffered_uarte::InterruptHandler<peripherals::UARTE0>;}, | ||||||
|     @irq SPIM0 = {SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 => spim::InterruptHandler<peripherals::TWISPI0>;}, |     @irq SPIM0 = {TWISPI0 => spim::InterruptHandler<peripherals::TWISPI0>;}, | ||||||
| ); | ); | ||||||
| 
 | 
 | ||||||
| #[cfg(feature = "nrf52833")] | #[cfg(feature = "nrf52833")] | ||||||
| @ -67,11 +67,11 @@ define_peris!( | |||||||
|     UART0 = UARTE0, |     UART0 = UARTE0, | ||||||
|     UART1 = UARTE1, |     UART1 = UARTE1, | ||||||
|     SPIM0 = TWISPI0, |     SPIM0 = TWISPI0, | ||||||
|     @irq UART0 = {UARTE0_UART0 => uarte::InterruptHandler<peripherals::UARTE0>;}, |     @irq UART0 = {UARTE0 => uarte::InterruptHandler<peripherals::UARTE0>;}, | ||||||
|     @irq UART1 = {UARTE1 => uarte::InterruptHandler<peripherals::UARTE1>;}, |     @irq UART1 = {UARTE1 => uarte::InterruptHandler<peripherals::UARTE1>;}, | ||||||
|     @irq UART0_BUFFERED = {UARTE0_UART0 => buffered_uarte::InterruptHandler<peripherals::UARTE0>;}, |     @irq UART0_BUFFERED = {UARTE0 => buffered_uarte::InterruptHandler<peripherals::UARTE0>;}, | ||||||
|     @irq UART1_BUFFERED = {UARTE1 => buffered_uarte::InterruptHandler<peripherals::UARTE1>;}, |     @irq UART1_BUFFERED = {UARTE1 => buffered_uarte::InterruptHandler<peripherals::UARTE1>;}, | ||||||
|     @irq SPIM0 = {SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 => spim::InterruptHandler<peripherals::TWISPI0>;}, |     @irq SPIM0 = {TWISPI0 => spim::InterruptHandler<peripherals::TWISPI0>;}, | ||||||
| ); | ); | ||||||
| 
 | 
 | ||||||
| #[cfg(feature = "nrf52840")] | #[cfg(feature = "nrf52840")] | ||||||
| @ -81,11 +81,11 @@ define_peris!( | |||||||
|     UART0 = UARTE0, |     UART0 = UARTE0, | ||||||
|     UART1 = UARTE1, |     UART1 = UARTE1, | ||||||
|     SPIM0 = TWISPI0, |     SPIM0 = TWISPI0, | ||||||
|     @irq UART0 = {UARTE0_UART0 => uarte::InterruptHandler<peripherals::UARTE0>;}, |     @irq UART0 = {UARTE0 => uarte::InterruptHandler<peripherals::UARTE0>;}, | ||||||
|     @irq UART1 = {UARTE1 => uarte::InterruptHandler<peripherals::UARTE1>;}, |     @irq UART1 = {UARTE1 => uarte::InterruptHandler<peripherals::UARTE1>;}, | ||||||
|     @irq UART0_BUFFERED = {UARTE0_UART0 => buffered_uarte::InterruptHandler<peripherals::UARTE0>;}, |     @irq UART0_BUFFERED = {UARTE0 => buffered_uarte::InterruptHandler<peripherals::UARTE0>;}, | ||||||
|     @irq UART1_BUFFERED = {UARTE1 => buffered_uarte::InterruptHandler<peripherals::UARTE1>;}, |     @irq UART1_BUFFERED = {UARTE1 => buffered_uarte::InterruptHandler<peripherals::UARTE1>;}, | ||||||
|     @irq SPIM0 = {SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 => spim::InterruptHandler<peripherals::TWISPI0>;}, |     @irq SPIM0 = {TWISPI0 => spim::InterruptHandler<peripherals::TWISPI0>;}, | ||||||
| ); | ); | ||||||
| 
 | 
 | ||||||
| #[cfg(feature = "nrf5340")] | #[cfg(feature = "nrf5340")] | ||||||
| @ -109,9 +109,9 @@ define_peris!( | |||||||
|     UART0 = SERIAL0, |     UART0 = SERIAL0, | ||||||
|     UART1 = SERIAL1, |     UART1 = SERIAL1, | ||||||
|     SPIM0 = SERIAL0, |     SPIM0 = SERIAL0, | ||||||
|     @irq UART0 = {UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 => uarte::InterruptHandler<peripherals::SERIAL0>;}, |     @irq UART0 = {SERIAL0 => uarte::InterruptHandler<peripherals::SERIAL0>;}, | ||||||
|     @irq UART1 = {UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 => uarte::InterruptHandler<peripherals::SERIAL1>;}, |     @irq UART1 = {SERIAL1 => uarte::InterruptHandler<peripherals::SERIAL1>;}, | ||||||
|     @irq UART0_BUFFERED = {UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 => buffered_uarte::InterruptHandler<peripherals::SERIAL0>;}, |     @irq UART0_BUFFERED = {SERIAL0 => buffered_uarte::InterruptHandler<peripherals::SERIAL0>;}, | ||||||
|     @irq UART1_BUFFERED = {UARTE1_SPIM1_SPIS1_TWIM1_TWIS1 => buffered_uarte::InterruptHandler<peripherals::SERIAL1>;}, |     @irq UART1_BUFFERED = {SERIAL1 => buffered_uarte::InterruptHandler<peripherals::SERIAL1>;}, | ||||||
|     @irq SPIM0 = {UARTE0_SPIM0_SPIS0_TWIM0_TWIS0 => spim::InterruptHandler<peripherals::SERIAL0>;}, |     @irq SPIM0 = {SERIAL0 => spim::InterruptHandler<peripherals::SERIAL0>;}, | ||||||
| ); | ); | ||||||
|  | |||||||
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