From f3703ff6bfed6f8342b49cfd9a65d543d1c99c27 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jan=20=C5=A0pa=C4=8Dek?= <patek.mail@gmail.com>
Date: Mon, 3 Jun 2024 20:12:33 +0200
Subject: [PATCH] stm32/usart: set refcount even if initialization failed

---
 embassy-stm32/src/usart/buffered.rs | 2 +-
 embassy-stm32/src/usart/mod.rs      | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index 09d020a7b..fd79e035e 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -315,6 +315,7 @@ impl<'d> BufferedUart<'d> {
     ) -> Result<(), ConfigError> {
         let info = self.rx.info;
         let state = self.rx.state;
+        state.tx_rx_refcount.store(2, Ordering::Relaxed);
 
         info.rcc.enable_and_reset();
 
@@ -339,7 +340,6 @@ impl<'d> BufferedUart<'d> {
         info.interrupt.unpend();
         unsafe { info.interrupt.enable() };
 
-        state.tx_rx_refcount.store(2, Ordering::Relaxed);
         Ok(())
     }
 
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index df5121f67..53321391a 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -446,6 +446,7 @@ impl<'d, M: Mode> UartTx<'d, M> {
     fn enable_and_configure(&mut self, config: &Config) -> Result<(), ConfigError> {
         let info = self.info;
         let state = self.state;
+        state.tx_rx_refcount.store(1, Ordering::Relaxed);
 
         info.rcc.enable_and_reset();
 
@@ -454,7 +455,6 @@ impl<'d, M: Mode> UartTx<'d, M> {
         });
         configure(info, self.kernel_clock, config, false, true)?;
 
-        state.tx_rx_refcount.store(1, Ordering::Relaxed);
         Ok(())
     }
 
@@ -798,6 +798,7 @@ impl<'d, M: Mode> UartRx<'d, M> {
     fn enable_and_configure(&mut self, config: &Config) -> Result<(), ConfigError> {
         let info = self.info;
         let state = self.state;
+        state.tx_rx_refcount.store(1, Ordering::Relaxed);
 
         info.rcc.enable_and_reset();
 
@@ -809,7 +810,6 @@ impl<'d, M: Mode> UartRx<'d, M> {
         info.interrupt.unpend();
         unsafe { info.interrupt.enable() };
 
-        state.tx_rx_refcount.store(1, Ordering::Relaxed);
         Ok(())
     }
 
@@ -1271,6 +1271,7 @@ impl<'d, M: Mode> Uart<'d, M> {
     fn enable_and_configure(&mut self, config: &Config) -> Result<(), ConfigError> {
         let info = self.rx.info;
         let state = self.rx.state;
+        state.tx_rx_refcount.store(2, Ordering::Relaxed);
 
         info.rcc.enable_and_reset();
 
@@ -1285,7 +1286,6 @@ impl<'d, M: Mode> Uart<'d, M> {
         info.interrupt.unpend();
         unsafe { info.interrupt.enable() };
 
-        state.tx_rx_refcount.store(2, Ordering::Relaxed);
         Ok(())
     }