From cbc7a9fe5b9bfda8a53316cd231d6a4b7a3bbfd9 Mon Sep 17 00:00:00 2001 From: Liu Hancheng Date: Wed, 1 Jan 2025 17:05:48 +0800 Subject: [PATCH 01/11] feat: Add 32-bit timer support for waveform function --- embassy-stm32/src/timer/low_level.rs | 4 +++ embassy-stm32/src/timer/simple_pwm.rs | 39 ++++++++++++++++++++------- 2 files changed, 34 insertions(+), 9 deletions(-) diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs index 7360d6aef..448069ab3 100644 --- a/embassy-stm32/src/timer/low_level.rs +++ b/embassy-stm32/src/timer/low_level.rs @@ -235,6 +235,10 @@ impl<'d, T: CoreInstance> Timer<'d, T> { self.regs_core().cnt().write(|r| r.set_cnt(0)); } + pub fn get_bits(&self) -> TimerBits { + T::BITS + } + /// Set the frequency of how many times per second the timer counts up to the max value or down to 0. /// /// This means that in the default edge-aligned mode, diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs index 56fb1871e..c6808593a 100644 --- a/embassy-stm32/src/timer/simple_pwm.rs +++ b/embassy-stm32/src/timer/simple_pwm.rs @@ -6,6 +6,7 @@ use core::mem::ManuallyDrop; use embassy_hal_internal::{into_ref, PeripheralRef}; use super::low_level::{CountingMode, OutputCompareMode, OutputPolarity, Timer}; +use super::TimerBits; use super::{Channel, Channel1Pin, Channel2Pin, Channel3Pin, Channel4Pin, GeneralInstance4Channel}; use crate::gpio::{AfType, AnyPin, OutputType, Speed}; use crate::time::Hertz; @@ -365,7 +366,7 @@ macro_rules! impl_waveform_chx { /// /// Note: /// you will need to provide corresponding TIMx_CHy DMA channel to use this method. - pub async fn $fn_name(&mut self, dma: impl Peripheral

>, duty: &[u16]) { + pub async fn $fn_name(&mut self, dma: impl Peripheral

>, duty: &[u8]) { use crate::pac::timer::vals::Ccds; into_ref!(dma); @@ -406,14 +407,34 @@ macro_rules! impl_waveform_chx { ..Default::default() }; - Transfer::new_write( - &mut dma, - req, - duty, - self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut _, - dma_transfer_option, - ) - .await + match self.inner.get_bits() { + TimerBits::Bits16 => { + // the data must be aligned to double words + assert!(duty.len() % 2 == 0); + let duty = core::slice::from_raw_parts(duty.as_ptr() as *const u16, duty.len() / 2); + Transfer::new_write( + &mut dma, + req, + duty, + self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut _, + dma_transfer_option, + ) + .await + } + TimerBits::Bits32 => { + // the data must be aligned to quad words + assert!(duty.len() % 4 == 0); + let duty = core::slice::from_raw_parts(duty.as_ptr() as *const u32, duty.len() / 4); + Transfer::new_write( + &mut dma, + req, + duty, + self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut _, + dma_transfer_option, + ) + .await + } + }; }; // restore output compare state From 89a1346d0098791cde9579597a13f2c059887094 Mon Sep 17 00:00:00 2001 From: Liu Hancheng Date: Wed, 1 Jan 2025 17:17:23 +0800 Subject: [PATCH 02/11] docs: Update PWM waveform function documentation for data alignment --- embassy-stm32/src/timer/simple_pwm.rs | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs index c6808593a..cce9f619a 100644 --- a/embassy-stm32/src/timer/simple_pwm.rs +++ b/embassy-stm32/src/timer/simple_pwm.rs @@ -365,7 +365,10 @@ macro_rules! impl_waveform_chx { /// Generate a sequence of PWM waveform /// /// Note: - /// you will need to provide corresponding TIMx_CHy DMA channel to use this method. + /// 1. you will need to provide corresponding TIMx_CHy DMA channel to use this method. + /// 2. Please make sure the duty data length is aligned to the timer data width(16-bit or 32-bit). + /// 3. Please notice the endianess of the duty data. STM32 use little endian, + /// for example, 0x12345678 as u32 will be stored as [0x78, 0x56, 0x34, 0x12] in memory. pub async fn $fn_name(&mut self, dma: impl Peripheral

>, duty: &[u8]) { use crate::pac::timer::vals::Ccds; From 99ce2853979a22e3f4573ea7f06db957a41f0a35 Mon Sep 17 00:00:00 2001 From: Liu Hancheng Date: Wed, 1 Jan 2025 17:21:33 +0800 Subject: [PATCH 03/11] refactor: change import style --- embassy-stm32/src/timer/simple_pwm.rs | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs index cce9f619a..e3c790213 100644 --- a/embassy-stm32/src/timer/simple_pwm.rs +++ b/embassy-stm32/src/timer/simple_pwm.rs @@ -6,8 +6,7 @@ use core::mem::ManuallyDrop; use embassy_hal_internal::{into_ref, PeripheralRef}; use super::low_level::{CountingMode, OutputCompareMode, OutputPolarity, Timer}; -use super::TimerBits; -use super::{Channel, Channel1Pin, Channel2Pin, Channel3Pin, Channel4Pin, GeneralInstance4Channel}; +use super::{Channel, Channel1Pin, Channel2Pin, Channel3Pin, Channel4Pin, GeneralInstance4Channel, TimerBits}; use crate::gpio::{AfType, AnyPin, OutputType, Speed}; use crate::time::Hertz; use crate::Peripheral; From e2c866119f941a1fa54e95b91076d1e299757bdb Mon Sep 17 00:00:00 2001 From: Liu Hancheng Date: Wed, 1 Jan 2025 17:24:00 +0800 Subject: [PATCH 04/11] doc: add doc for timer get_bits fn --- embassy-stm32/src/timer/low_level.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs index 448069ab3..a9c6dc303 100644 --- a/embassy-stm32/src/timer/low_level.rs +++ b/embassy-stm32/src/timer/low_level.rs @@ -235,6 +235,7 @@ impl<'d, T: CoreInstance> Timer<'d, T> { self.regs_core().cnt().write(|r| r.set_cnt(0)); } + /// get the capability of the timer pub fn get_bits(&self) -> TimerBits { T::BITS } From a3a8dee57906bffdd2a6f29c46abab48bfe0b2c3 Mon Sep 17 00:00:00 2001 From: Liu Hancheng Date: Wed, 1 Jan 2025 17:28:37 +0800 Subject: [PATCH 05/11] refactor: exclude stm32l0 for 32bit timer branch Signed-off-by: Liu Hancheng --- embassy-stm32/src/timer/simple_pwm.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs index e3c790213..0fc2a1bf0 100644 --- a/embassy-stm32/src/timer/simple_pwm.rs +++ b/embassy-stm32/src/timer/simple_pwm.rs @@ -423,6 +423,7 @@ macro_rules! impl_waveform_chx { ) .await } + #[cfg(not(stm32l0))] TimerBits::Bits32 => { // the data must be aligned to quad words assert!(duty.len() % 4 == 0); From 90b41644261440a535c35c1c75c22ce2606c5037 Mon Sep 17 00:00:00 2001 From: Liu Hancheng Date: Thu, 2 Jan 2025 12:47:13 +0800 Subject: [PATCH 06/11] dev: change name to bits --- embassy-stm32/src/timer/low_level.rs | 2 +- embassy-stm32/src/timer/simple_pwm.rs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs index a9c6dc303..796c33a27 100644 --- a/embassy-stm32/src/timer/low_level.rs +++ b/embassy-stm32/src/timer/low_level.rs @@ -236,7 +236,7 @@ impl<'d, T: CoreInstance> Timer<'d, T> { } /// get the capability of the timer - pub fn get_bits(&self) -> TimerBits { + pub fn bits(&self) -> TimerBits { T::BITS } diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs index 0fc2a1bf0..f36fa026c 100644 --- a/embassy-stm32/src/timer/simple_pwm.rs +++ b/embassy-stm32/src/timer/simple_pwm.rs @@ -409,7 +409,7 @@ macro_rules! impl_waveform_chx { ..Default::default() }; - match self.inner.get_bits() { + match self.inner.bits() { TimerBits::Bits16 => { // the data must be aligned to double words assert!(duty.len() % 2 == 0); From ff526e1604f4e9edc682f4bc270ddc815a860e48 Mon Sep 17 00:00:00 2001 From: Liu Hancheng Date: Sat, 4 Jan 2025 20:16:34 +0800 Subject: [PATCH 07/11] refactor: update DMA transfer functions to use separate memory and peripheral sizes --- embassy-stm32/src/dma/dma_bdma.rs | 38 ++++++++++++++++++--------- embassy-stm32/src/timer/simple_pwm.rs | 26 +++++++----------- 2 files changed, 35 insertions(+), 29 deletions(-) diff --git a/embassy-stm32/src/dma/dma_bdma.rs b/embassy-stm32/src/dma/dma_bdma.rs index 1945c3587..8b4b454c0 100644 --- a/embassy-stm32/src/dma/dma_bdma.rs +++ b/embassy-stm32/src/dma/dma_bdma.rs @@ -340,7 +340,8 @@ impl AnyChannel { mem_addr: *mut u32, mem_len: usize, incr_mem: bool, - data_size: WordSize, + mem_size: WordSize, + peripheral_size: WordSize, options: TransferOptions, ) { let info = self.info(); @@ -380,8 +381,8 @@ impl AnyChannel { }); ch.cr().write(|w| { w.set_dir(dir.into()); - w.set_msize(data_size.into()); - w.set_psize(data_size.into()); + w.set_msize(mem_size.into()); + w.set_psize(peripheral_size.into()); w.set_pl(options.priority.into()); w.set_minc(incr_mem); w.set_pinc(false); @@ -414,8 +415,8 @@ impl AnyChannel { ch.mar().write_value(mem_addr as u32); ch.ndtr().write(|w| w.set_ndt(mem_len as u16)); ch.cr().write(|w| { - w.set_psize(data_size.into()); - w.set_msize(data_size.into()); + w.set_psize(peripheral_size.into()); + w.set_msize(mem_size.into()); w.set_minc(incr_mem); w.set_dir(dir.into()); w.set_teie(true); @@ -602,27 +603,28 @@ impl<'a> Transfer<'a> { buf.len(), true, W::size(), + W::size(), options, ) } /// Create a new write DMA transfer (memory to peripheral). - pub unsafe fn new_write( + pub unsafe fn new_write( channel: impl Peripheral

+ 'a, request: Request, - buf: &'a [W], - peri_addr: *mut W, + buf: &'a [MW], + peri_addr: *mut PW, options: TransferOptions, ) -> Self { Self::new_write_raw(channel, request, buf, peri_addr, options) } /// Create a new write DMA transfer (memory to peripheral), using raw pointers. - pub unsafe fn new_write_raw( + pub unsafe fn new_write_raw( channel: impl Peripheral

+ 'a, request: Request, buf: *const [W], - peri_addr: *mut W, + peri_addr: *mut PW, options: TransferOptions, ) -> Self { into_ref!(channel); @@ -636,6 +638,7 @@ impl<'a> Transfer<'a> { buf.len(), true, W::size(), + W::size(), options, ) } @@ -660,6 +663,7 @@ impl<'a> Transfer<'a> { count, false, W::size(), + W::size(), options, ) } @@ -673,15 +677,23 @@ impl<'a> Transfer<'a> { mem_len: usize, incr_mem: bool, data_size: WordSize, + peripheral_size: WordSize, options: TransferOptions, ) -> Self { assert!(mem_len > 0 && mem_len <= 0xFFFF); channel.configure( - _request, dir, peri_addr, mem_addr, mem_len, incr_mem, data_size, options, + _request, + dir, + peri_addr, + mem_addr, + mem_len, + incr_mem, + data_size, + peripheral_size, + options, ); channel.start(); - Self { channel } } @@ -814,6 +826,7 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W> { len, true, data_size, + data_size, options, ); @@ -966,6 +979,7 @@ impl<'a, W: Word> WritableRingBuffer<'a, W> { len, true, data_size, + data_size, options, ); diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs index f36fa026c..8d3c9a131 100644 --- a/embassy-stm32/src/timer/simple_pwm.rs +++ b/embassy-stm32/src/timer/simple_pwm.rs @@ -334,7 +334,7 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> { &mut dma, req, duty, - self.inner.regs_1ch().ccr(channel.index()).as_ptr() as *mut _, + self.inner.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16, dma_transfer_option, ) .await @@ -362,13 +362,7 @@ macro_rules! impl_waveform_chx { ($fn_name:ident, $dma_ch:ident, $cc_ch:ident) => { impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> { /// Generate a sequence of PWM waveform - /// - /// Note: - /// 1. you will need to provide corresponding TIMx_CHy DMA channel to use this method. - /// 2. Please make sure the duty data length is aligned to the timer data width(16-bit or 32-bit). - /// 3. Please notice the endianess of the duty data. STM32 use little endian, - /// for example, 0x12345678 as u32 will be stored as [0x78, 0x56, 0x34, 0x12] in memory. - pub async fn $fn_name(&mut self, dma: impl Peripheral

>, duty: &[u8]) { + pub async fn $fn_name(&mut self, dma: impl Peripheral

>, duty: &[u16]) { use crate::pac::timer::vals::Ccds; into_ref!(dma); @@ -411,32 +405,30 @@ macro_rules! impl_waveform_chx { match self.inner.bits() { TimerBits::Bits16 => { - // the data must be aligned to double words - assert!(duty.len() % 2 == 0); - let duty = core::slice::from_raw_parts(duty.as_ptr() as *const u16, duty.len() / 2); Transfer::new_write( &mut dma, req, duty, - self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut _, + self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u16, dma_transfer_option, ) .await } - #[cfg(not(stm32l0))] + #[cfg(not(any(stm32l0, bdma, gpdma)))] TimerBits::Bits32 => { - // the data must be aligned to quad words - assert!(duty.len() % 4 == 0); - let duty = core::slice::from_raw_parts(duty.as_ptr() as *const u32, duty.len() / 4); Transfer::new_write( &mut dma, req, duty, - self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut _, + self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u32, dma_transfer_option, ) .await } + #[cfg(any(stm32l0, bdma, gpdma))] + _ => { + panic!("unsupported timer bits") + } }; }; From 7d74d15b184a58f010551571051055ce9ca0023a Mon Sep 17 00:00:00 2001 From: Liu Hancheng Date: Sat, 4 Jan 2025 21:10:32 +0800 Subject: [PATCH 08/11] refactor: update DMA pointer types for cryp and hash modules --- embassy-stm32/src/cryp/mod.rs | 8 ++++---- embassy-stm32/src/hash/mod.rs | 15 +++++++++++---- 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs index 8d600c73c..6afe68a39 100644 --- a/embassy-stm32/src/cryp/mod.rs +++ b/embassy-stm32/src/cryp/mod.rs @@ -1785,9 +1785,9 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> { assert_eq!(blocks.len() % block_size, 0); // Configure DMA to transfer input to crypto core. let dma_request = dma.request(); - let dst_ptr = T::regs().din().as_ptr(); + let dst_ptr: *mut u32 = T::regs().din().as_ptr(); let num_words = blocks.len() / 4; - let src_ptr = ptr::slice_from_raw_parts(blocks.as_ptr().cast(), num_words); + let src_ptr: *const [u8] = ptr::slice_from_raw_parts(blocks.as_ptr().cast(), num_words); let options = TransferOptions { #[cfg(not(gpdma))] priority: crate::dma::Priority::High, @@ -1825,9 +1825,9 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> { assert_eq!((blocks.len() * 4) % block_size, 0); // Configure DMA to transfer input to crypto core. let dma_request = dma.request(); - let dst_ptr = T::regs().din().as_ptr(); + let dst_ptr: *mut u32 = T::regs().din().as_ptr(); let num_words = blocks.len(); - let src_ptr = ptr::slice_from_raw_parts(blocks.as_ptr().cast(), num_words); + let src_ptr: *const [u32] = ptr::slice_from_raw_parts(blocks.as_ptr().cast(), num_words); let options = TransferOptions { #[cfg(not(gpdma))] priority: crate::dma::Priority::High, diff --git a/embassy-stm32/src/hash/mod.rs b/embassy-stm32/src/hash/mod.rs index 4d4a8ec5b..3c2125498 100644 --- a/embassy-stm32/src/hash/mod.rs +++ b/embassy-stm32/src/hash/mod.rs @@ -515,14 +515,21 @@ impl<'d, T: Instance, D> Hash<'d, T, D> { // Configure DMA to transfer input to hash core. let dma_request = self.dma.request(); - let dst_ptr = T::regs().din().as_ptr(); + let dst_ptr: *mut u32 = T::regs().din().as_ptr(); let mut num_words = input.len() / 4; if input.len() % 4 > 0 { num_words += 1; } - let src_ptr = ptr::slice_from_raw_parts(input.as_ptr().cast(), num_words); - let dma_transfer = - unsafe { Transfer::new_write_raw(&mut self.dma, dma_request, src_ptr, dst_ptr, Default::default()) }; + let src_ptr: *const [u8] = ptr::slice_from_raw_parts(input.as_ptr().cast(), num_words); + let dma_transfer = unsafe { + Transfer::new_write_raw( + &mut self.dma, + dma_request, + src_ptr, + dst_ptr as *mut u32, + Default::default(), + ) + }; T::regs().cr().modify(|w| w.set_dmae(true)); // Wait for the transfer to complete. From 03dd50316c6f41a2bfab62289aa22abdaaa3189d Mon Sep 17 00:00:00 2001 From: Liu Hancheng Date: Sat, 4 Jan 2025 21:38:22 +0800 Subject: [PATCH 09/11] refactor: simplify timer bits handling --- embassy-stm32/src/timer/simple_pwm.rs | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs index 8d3c9a131..757536c2d 100644 --- a/embassy-stm32/src/timer/simple_pwm.rs +++ b/embassy-stm32/src/timer/simple_pwm.rs @@ -414,8 +414,10 @@ macro_rules! impl_waveform_chx { ) .await } - #[cfg(not(any(stm32l0, bdma, gpdma)))] + #[cfg(not(any(stm32l0)))] TimerBits::Bits32 => { + #[cfg(any(bdma, gpdma))] + panic("unsupported timer bits"); Transfer::new_write( &mut dma, req, @@ -425,10 +427,6 @@ macro_rules! impl_waveform_chx { ) .await } - #[cfg(any(stm32l0, bdma, gpdma))] - _ => { - panic!("unsupported timer bits") - } }; }; From 50e98a9a58bf7f3356aa8261ba301d4d1c6440aa Mon Sep 17 00:00:00 2001 From: Liu Hancheng Date: Sat, 4 Jan 2025 22:10:47 +0800 Subject: [PATCH 10/11] refactor: update DMA transfer functions to support separate memory and peripheral word types --- embassy-stm32/src/dma/gpdma.rs | 32 +++++++++++++++------------ embassy-stm32/src/timer/simple_pwm.rs | 4 +++- 2 files changed, 21 insertions(+), 15 deletions(-) diff --git a/embassy-stm32/src/dma/gpdma.rs b/embassy-stm32/src/dma/gpdma.rs index a877bb8d4..e57bf04ed 100644 --- a/embassy-stm32/src/dma/gpdma.rs +++ b/embassy-stm32/src/dma/gpdma.rs @@ -143,27 +143,28 @@ impl<'a> Transfer<'a> { buf.len(), true, W::size(), + W::size(), options, ) } /// Create a new write DMA transfer (memory to peripheral). - pub unsafe fn new_write( + pub unsafe fn new_write( channel: impl Peripheral

+ 'a, request: Request, - buf: &'a [W], - peri_addr: *mut W, + buf: &'a [MW], + peri_addr: *mut PW, options: TransferOptions, ) -> Self { Self::new_write_raw(channel, request, buf, peri_addr, options) } /// Create a new write DMA transfer (memory to peripheral), using raw pointers. - pub unsafe fn new_write_raw( + pub unsafe fn new_write_raw( channel: impl Peripheral

+ 'a, request: Request, - buf: *const [W], - peri_addr: *mut W, + buf: *const [MW], + peri_addr: *mut PW, options: TransferOptions, ) -> Self { into_ref!(channel); @@ -173,21 +174,22 @@ impl<'a> Transfer<'a> { request, Dir::MemoryToPeripheral, peri_addr as *const u32, - buf as *const W as *mut u32, + buf as *const MW as *mut u32, buf.len(), true, - W::size(), + MW::size(), + PW::size(), options, ) } /// Create a new write DMA transfer (memory to peripheral), writing the same value repeatedly. - pub unsafe fn new_write_repeated( + pub unsafe fn new_write_repeated( channel: impl Peripheral

+ 'a, request: Request, - repeated: &'a W, + repeated: &'a MW, count: usize, - peri_addr: *mut W, + peri_addr: *mut PW, options: TransferOptions, ) -> Self { into_ref!(channel); @@ -197,10 +199,11 @@ impl<'a> Transfer<'a> { request, Dir::MemoryToPeripheral, peri_addr as *const u32, - repeated as *const W as *mut u32, + repeated as *const MW as *mut u32, count, false, - W::size(), + MW::size(), + PW::size(), options, ) } @@ -214,6 +217,7 @@ impl<'a> Transfer<'a> { mem_len: usize, incr_mem: bool, data_size: WordSize, + dst_size: WordSize, _options: TransferOptions, ) -> Self { // BNDT is specified as bytes, not as number of transfers. @@ -234,7 +238,7 @@ impl<'a> Transfer<'a> { ch.llr().write(|_| {}); // no linked list ch.tr1().write(|w| { w.set_sdw(data_size.into()); - w.set_ddw(data_size.into()); + w.set_ddw(dst_size.into()); w.set_sinc(dir == Dir::MemoryToPeripheral && incr_mem); w.set_dinc(dir == Dir::PeripheralToMemory && incr_mem); }); diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs index 757536c2d..5b3cf8fea 100644 --- a/embassy-stm32/src/timer/simple_pwm.rs +++ b/embassy-stm32/src/timer/simple_pwm.rs @@ -416,8 +416,10 @@ macro_rules! impl_waveform_chx { } #[cfg(not(any(stm32l0)))] TimerBits::Bits32 => { + #[cfg(not(any(bdma, gpdma)))] + panic!("unsupported timer bits"); + #[cfg(any(bdma, gpdma))] - panic("unsupported timer bits"); Transfer::new_write( &mut dma, req, From 4ad3b66e453971c3df44945dbe1d7815dae81d9e Mon Sep 17 00:00:00 2001 From: Liu Hancheng Date: Sun, 5 Jan 2025 10:25:10 +0800 Subject: [PATCH 11/11] refactor: update write DMA transfer function to use separate memory word type --- embassy-stm32/src/dma/dma_bdma.rs | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/embassy-stm32/src/dma/dma_bdma.rs b/embassy-stm32/src/dma/dma_bdma.rs index 8b4b454c0..fa32bd8cb 100644 --- a/embassy-stm32/src/dma/dma_bdma.rs +++ b/embassy-stm32/src/dma/dma_bdma.rs @@ -620,10 +620,10 @@ impl<'a> Transfer<'a> { } /// Create a new write DMA transfer (memory to peripheral), using raw pointers. - pub unsafe fn new_write_raw( + pub unsafe fn new_write_raw( channel: impl Peripheral

+ 'a, request: Request, - buf: *const [W], + buf: *const [MW], peri_addr: *mut PW, options: TransferOptions, ) -> Self { @@ -634,11 +634,11 @@ impl<'a> Transfer<'a> { request, Dir::MemoryToPeripheral, peri_addr as *const u32, - buf as *const W as *mut u32, + buf as *const MW as *mut u32, buf.len(), true, - W::size(), - W::size(), + MW::size(), + PW::size(), options, ) }