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chore: fix build

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This commit is contained in:
elagil 2025-01-03 18:18:00 +01:00
parent 96819805ea
commit eba8089601
34 changed files with 191 additions and 185 deletions
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8
embassy-stm32/src/adc/g4.rs
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@ -178,14 +178,14 @@ impl<'d, T: Instance> Adc<'d, T> {
fn configure_differential_inputs(&mut self) { fn configure_differential_inputs(&mut self) {
T::regs().difsel().modify(|w| { T::regs().difsel().modify(|w| {
for n in 0..18 { for n in 0..18 {
w.set_difsel(n, Difsel::SINGLEENDED); w.set_difsel(n, Difsel::SINGLE_ENDED);
} }
}); });
} }
fn calibrate(&mut self) { fn calibrate(&mut self) {
T::regs().cr().modify(|w| { T::regs().cr().modify(|w| {
w.set_adcaldif(Adcaldif::SINGLEENDED); w.set_adcaldif(Adcaldif::SINGLE_ENDED);
}); });
T::regs().cr().modify(|w| w.set_adcal(true)); T::regs().cr().modify(|w| w.set_adcal(true));
@ -266,7 +266,7 @@ impl<'d, T: Instance> Adc<'d, T> {
if enable { if enable {
Difsel::DIFFERENTIAL Difsel::DIFFERENTIAL
} else { } else {
Difsel::SINGLEENDED Difsel::SINGLE_ENDED
}, },
); );
}); });
@ -435,7 +435,7 @@ impl<'d, T: Instance> Adc<'d, T> {
T::regs().cfgr().modify(|reg| { T::regs().cfgr().modify(|reg| {
reg.set_discen(false); reg.set_discen(false);
reg.set_cont(true); reg.set_cont(true);
reg.set_dmacfg(Dmacfg::ONESHOT); reg.set_dmacfg(Dmacfg::ONE_SHOT);
reg.set_dmaen(Dmaen::ENABLE); reg.set_dmaen(Dmaen::ENABLE);
}); });

2
embassy-stm32/src/adc/ringbuffered_v2.rs
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@ -312,7 +312,7 @@ impl<'d, T: Instance> RingBufferedAdc<'d, T> {
// DMA requests are issues as long as DMA=1 and data are converted. // DMA requests are issues as long as DMA=1 and data are converted.
w.set_dds(vals::Dds::CONTINUOUS); w.set_dds(vals::Dds::CONTINUOUS);
// EOC flag is set at the end of each conversion. // EOC flag is set at the end of each conversion.
w.set_eocs(vals::Eocs::EACHCONVERSION); w.set_eocs(vals::Eocs::EACH_CONVERSION);
}); });
// Begin ADC conversions // Begin ADC conversions

2
embassy-stm32/src/adc/u5_adc4.rs
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@ -416,7 +416,7 @@ impl<'d, T: Instance> Adc4<'d, T> {
T::regs().cfgr1().modify(|reg| { T::regs().cfgr1().modify(|reg| {
reg.set_dmaen(true); reg.set_dmaen(true);
reg.set_dmacfg(Adc4Dmacfg::ONESHOT); reg.set_dmacfg(Adc4Dmacfg::ONE_SHOT);
reg.set_chselrmod(false); reg.set_chselrmod(false);
}); });

2
embassy-stm32/src/adc/v1.rs
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@ -160,7 +160,7 @@ impl<'d, T: Instance> Adc<'d, T> {
channel.setup(); channel.setup();
// A.7.5 Single conversion sequence code example - Software trigger // A.7.5 Single conversion sequence code example - Software trigger
T::regs().chselr().write(|reg| reg.set_chselx(ch_num as usize, true)); T::regs().chselr().write(|reg| reg.set_chsel_x(ch_num as usize, true));
self.convert().await self.convert().await
} }

4
embassy-stm32/src/adc/v3.rs
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@ -366,14 +366,14 @@ impl<'d, T: Instance> Adc<'d, T> {
T::regs().cfgr().modify(|reg| { T::regs().cfgr().modify(|reg| {
reg.set_discen(false); reg.set_discen(false);
reg.set_cont(true); reg.set_cont(true);
reg.set_dmacfg(Dmacfg::ONESHOT); reg.set_dmacfg(Dmacfg::ONE_SHOT);
reg.set_dmaen(true); reg.set_dmaen(true);
}); });
#[cfg(any(adc_g0, adc_u0))] #[cfg(any(adc_g0, adc_u0))]
T::regs().cfgr1().modify(|reg| { T::regs().cfgr1().modify(|reg| {
reg.set_discen(false); reg.set_discen(false);
reg.set_cont(true); reg.set_cont(true);
reg.set_dmacfg(Dmacfg::ONESHOT); reg.set_dmacfg(Dmacfg::ONE_SHOT);
reg.set_dmaen(true); reg.set_dmaen(true);
}); });

6
embassy-stm32/src/adc/v4.rs
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@ -214,7 +214,7 @@ impl<'d, T: Instance> Adc<'d, T> {
fn configure_differential_inputs(&mut self) { fn configure_differential_inputs(&mut self) {
T::regs().difsel().modify(|w| { T::regs().difsel().modify(|w| {
for n in 0..20 { for n in 0..20 {
w.set_difsel(n, Difsel::SINGLEENDED); w.set_difsel(n, Difsel::SINGLE_ENDED);
} }
}); });
} }
@ -222,7 +222,7 @@ impl<'d, T: Instance> Adc<'d, T> {
fn calibrate(&mut self) { fn calibrate(&mut self) {
T::regs().cr().modify(|w| { T::regs().cr().modify(|w| {
#[cfg(not(adc_u5))] #[cfg(not(adc_u5))]
w.set_adcaldif(Adcaldif::SINGLEENDED); w.set_adcaldif(Adcaldif::SINGLE_ENDED);
w.set_adcallin(true); w.set_adcallin(true);
}); });
@ -420,7 +420,7 @@ impl<'d, T: Instance> Adc<'d, T> {
}); });
T::regs().cfgr().modify(|reg| { T::regs().cfgr().modify(|reg| {
reg.set_cont(true); reg.set_cont(true);
reg.set_dmngt(Dmngt::DMA_ONESHOT); reg.set_dmngt(Dmngt::DMA_ONE_SHOT);
}); });
let request = rx_dma.request(); let request = rx_dma.request();

8
embassy-stm32/src/can/bxcan/registers.rs
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@ -166,16 +166,16 @@ impl Registers {
return Some(BusError::BusPassive); return Some(BusError::BusPassive);
} else if err.ewgf() { } else if err.ewgf() {
return Some(BusError::BusWarning); return Some(BusError::BusWarning);
} else if err.lec() != Lec::NOERROR { } else if err.lec() != Lec::NO_ERROR {
return Some(match err.lec() { return Some(match err.lec() {
Lec::STUFF => BusError::Stuff, Lec::STUFF => BusError::Stuff,
Lec::FORM => BusError::Form, Lec::FORM => BusError::Form,
Lec::ACK => BusError::Acknowledge, Lec::ACK => BusError::Acknowledge,
Lec::BITRECESSIVE => BusError::BitRecessive, Lec::BIT_RECESSIVE => BusError::BitRecessive,
Lec::BITDOMINANT => BusError::BitDominant, Lec::BIT_DOMINANT => BusError::BitDominant,
Lec::CRC => BusError::Crc, Lec::CRC => BusError::Crc,
Lec::CUSTOM => BusError::Software, Lec::CUSTOM => BusError::Software,
Lec::NOERROR => unreachable!(), Lec::NO_ERROR => unreachable!(),
}); });
} }
None None

2
embassy-stm32/src/crc/v2v3.rs
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@ -118,7 +118,7 @@ impl<'d> Crc<'d> {
w.set_rev_in(match self._config.reverse_in { w.set_rev_in(match self._config.reverse_in {
InputReverseConfig::None => vals::RevIn::NORMAL, InputReverseConfig::None => vals::RevIn::NORMAL,
InputReverseConfig::Byte => vals::RevIn::BYTE, InputReverseConfig::Byte => vals::RevIn::BYTE,
InputReverseConfig::Halfword => vals::RevIn::HALFWORD, InputReverseConfig::Halfword => vals::RevIn::HALF_WORD,
InputReverseConfig::Word => vals::RevIn::WORD, InputReverseConfig::Word => vals::RevIn::WORD,
}); });
// configure the polynomial. // configure the polynomial.

14
embassy-stm32/src/dma/dma_bdma.rs
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@ -100,7 +100,7 @@ impl From<Priority> for pac::dma::vals::Pl {
Priority::Low => pac::dma::vals::Pl::LOW, Priority::Low => pac::dma::vals::Pl::LOW,
Priority::Medium => pac::dma::vals::Pl::MEDIUM, Priority::Medium => pac::dma::vals::Pl::MEDIUM,
Priority::High => pac::dma::vals::Pl::HIGH, Priority::High => pac::dma::vals::Pl::HIGH,
Priority::VeryHigh => pac::dma::vals::Pl::VERYHIGH, Priority::VeryHigh => pac::dma::vals::Pl::VERY_HIGH,
} }
} }
} }
@ -112,7 +112,7 @@ impl From<Priority> for pac::bdma::vals::Pl {
Priority::Low => pac::bdma::vals::Pl::LOW, Priority::Low => pac::bdma::vals::Pl::LOW,
Priority::Medium => pac::bdma::vals::Pl::MEDIUM, Priority::Medium => pac::bdma::vals::Pl::MEDIUM,
Priority::High => pac::bdma::vals::Pl::HIGH, Priority::High => pac::bdma::vals::Pl::HIGH,
Priority::VeryHigh => pac::bdma::vals::Pl::VERYHIGH, Priority::VeryHigh => pac::bdma::vals::Pl::VERY_HIGH,
} }
} }
} }
@ -138,8 +138,8 @@ mod dma_only {
impl From<Dir> for vals::Dir { impl From<Dir> for vals::Dir {
fn from(raw: Dir) -> Self { fn from(raw: Dir) -> Self {
match raw { match raw {
Dir::MemoryToPeripheral => Self::MEMORYTOPERIPHERAL, Dir::MemoryToPeripheral => Self::MEMORY_TO_PERIPHERAL,
Dir::PeripheralToMemory => Self::PERIPHERALTOMEMORY, Dir::PeripheralToMemory => Self::PERIPHERAL_TO_MEMORY,
} }
} }
} }
@ -207,7 +207,7 @@ mod dma_only {
match value { match value {
FifoThreshold::Quarter => vals::Fth::QUARTER, FifoThreshold::Quarter => vals::Fth::QUARTER,
FifoThreshold::Half => vals::Fth::HALF, FifoThreshold::Half => vals::Fth::HALF,
FifoThreshold::ThreeQuarters => vals::Fth::THREEQUARTERS, FifoThreshold::ThreeQuarters => vals::Fth::THREE_QUARTERS,
FifoThreshold::Full => vals::Fth::FULL, FifoThreshold::Full => vals::Fth::FULL,
} }
} }
@ -233,8 +233,8 @@ mod bdma_only {
impl From<Dir> for vals::Dir { impl From<Dir> for vals::Dir {
fn from(raw: Dir) -> Self { fn from(raw: Dir) -> Self {
match raw { match raw {
Dir::MemoryToPeripheral => Self::FROMMEMORY, Dir::MemoryToPeripheral => Self::FROM_MEMORY,
Dir::PeripheralToMemory => Self::FROMPERIPHERAL, Dir::PeripheralToMemory => Self::FROM_PERIPHERAL,
} }
} }
} }

6
embassy-stm32/src/dma/gpdma.rs
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@ -38,7 +38,7 @@ impl From<WordSize> for vals::Dw {
fn from(raw: WordSize) -> Self { fn from(raw: WordSize) -> Self {
match raw { match raw {
WordSize::OneByte => Self::BYTE, WordSize::OneByte => Self::BYTE,
WordSize::TwoBytes => Self::HALFWORD, WordSize::TwoBytes => Self::HALF_WORD,
WordSize::FourBytes => Self::WORD, WordSize::FourBytes => Self::WORD,
} }
} }
@ -240,8 +240,8 @@ impl<'a> Transfer<'a> {
}); });
ch.tr2().write(|w| { ch.tr2().write(|w| {
w.set_dreq(match dir { w.set_dreq(match dir {
Dir::MemoryToPeripheral => vals::Dreq::DESTINATIONPERIPHERAL, Dir::MemoryToPeripheral => vals::Dreq::DESTINATION_PERIPHERAL,
Dir::PeripheralToMemory => vals::Dreq::SOURCEPERIPHERAL, Dir::PeripheralToMemory => vals::Dreq::SOURCE_PERIPHERAL,
}); });
w.set_reqsel(request); w.set_reqsel(request);
}); });

8
embassy-stm32/src/eth/v1/mod.rs
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@ -159,8 +159,8 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
w.set_ifg(Ifg::IFG96); // inter frame gap 96 bit times w.set_ifg(Ifg::IFG96); // inter frame gap 96 bit times
w.set_apcs(Apcs::STRIP); // automatic padding and crc stripping w.set_apcs(Apcs::STRIP); // automatic padding and crc stripping
w.set_fes(Fes::FES100); // fast ethernet speed w.set_fes(Fes::FES100); // fast ethernet speed
w.set_dm(Dm::FULLDUPLEX); // full duplex w.set_dm(Dm::FULL_DUPLEX); // full duplex
// TODO: Carrier sense ? ECRSFD // TODO: Carrier sense ? ECRSFD
}); });
// Set the mac to pass all multicast packets // Set the mac to pass all multicast packets
@ -186,8 +186,8 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
// Transfer and Forward, Receive and Forward // Transfer and Forward, Receive and Forward
dma.dmaomr().modify(|w| { dma.dmaomr().modify(|w| {
w.set_tsf(Tsf::STOREFORWARD); w.set_tsf(Tsf::STORE_FORWARD);
w.set_rsf(Rsf::STOREFORWARD); w.set_rsf(Rsf::STORE_FORWARD);
}); });
dma.dmabmr().modify(|w| { dma.dmabmr().modify(|w| {

6
embassy-stm32/src/eth/v1/rx_desc.rs
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@ -168,15 +168,15 @@ impl<'a> RDesRing<'a> {
// Reset or Stop Receive Command issued // Reset or Stop Receive Command issued
Rps::STOPPED => RunningState::Stopped, Rps::STOPPED => RunningState::Stopped,
// Fetching receive transfer descriptor // Fetching receive transfer descriptor
Rps::RUNNINGFETCHING => RunningState::Running, Rps::RUNNING_FETCHING => RunningState::Running,
// Waiting for receive packet // Waiting for receive packet
Rps::RUNNINGWAITING => RunningState::Running, Rps::RUNNING_WAITING => RunningState::Running,
// Receive descriptor unavailable // Receive descriptor unavailable
Rps::SUSPENDED => RunningState::Stopped, Rps::SUSPENDED => RunningState::Stopped,
// Closing receive descriptor // Closing receive descriptor
Rps::_RESERVED_5 => RunningState::Running, Rps::_RESERVED_5 => RunningState::Running,
// Transferring the receive packet data from receive buffer to host memory // Transferring the receive packet data from receive buffer to host memory
Rps::RUNNINGWRITING => RunningState::Running, Rps::RUNNING_WRITING => RunningState::Running,
_ => RunningState::Unknown, _ => RunningState::Unknown,
} }
} }

2
embassy-stm32/src/flash/f4.rs
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@ -469,7 +469,7 @@ fn pa12_is_output_pull_low() -> bool {
use pac::GPIOA; use pac::GPIOA;
const PIN: usize = 12; const PIN: usize = 12;
GPIOA.moder().read().moder(PIN) == vals::Moder::OUTPUT GPIOA.moder().read().moder(PIN) == vals::Moder::OUTPUT
&& GPIOA.pupdr().read().pupdr(PIN) == vals::Pupdr::PULLDOWN && GPIOA.pupdr().read().pupdr(PIN) == vals::Pupdr::PULL_DOWN
&& GPIOA.odr().read().odr(PIN) == vals::Odr::LOW && GPIOA.odr().read().odr(PIN) == vals::Odr::LOW
} }

38
embassy-stm32/src/gpio.rs
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@ -61,7 +61,7 @@ impl<'d> Flex<'d> {
#[cfg(gpio_v2)] #[cfg(gpio_v2)]
{ {
r.pupdr().modify(|w| w.set_pupdr(n, pull.to_pupdr())); r.pupdr().modify(|w| w.set_pupdr(n, pull.to_pupdr()));
r.otyper().modify(|w| w.set_ot(n, vals::Ot::PUSHPULL)); r.otyper().modify(|w| w.set_ot(n, vals::Ot::PUSH_PULL));
r.moder().modify(|w| w.set_moder(n, vals::Moder::INPUT)); r.moder().modify(|w| w.set_moder(n, vals::Moder::INPUT));
} }
}); });
@ -82,13 +82,13 @@ impl<'d> Flex<'d> {
{ {
r.cr(n / 8).modify(|w| { r.cr(n / 8).modify(|w| {
w.set_mode(n % 8, speed.to_mode()); w.set_mode(n % 8, speed.to_mode());
w.set_cnf_out(n % 8, vals::CnfOut::PUSHPULL); w.set_cnf_out(n % 8, vals::CnfOut::PUSH_PULL);
}); });
} }
#[cfg(gpio_v2)] #[cfg(gpio_v2)]
{ {
r.pupdr().modify(|w| w.set_pupdr(n, vals::Pupdr::FLOATING)); r.pupdr().modify(|w| w.set_pupdr(n, vals::Pupdr::FLOATING));
r.otyper().modify(|w| w.set_ot(n, vals::Ot::PUSHPULL)); r.otyper().modify(|w| w.set_ot(n, vals::Ot::PUSH_PULL));
r.ospeedr().modify(|w| w.set_ospeedr(n, speed.to_ospeedr())); r.ospeedr().modify(|w| w.set_ospeedr(n, speed.to_ospeedr()));
r.moder().modify(|w| w.set_moder(n, vals::Moder::OUTPUT)); r.moder().modify(|w| w.set_moder(n, vals::Moder::OUTPUT));
} }
@ -112,7 +112,7 @@ impl<'d> Flex<'d> {
let r = self.pin.block(); let r = self.pin.block();
let n = self.pin.pin() as usize; let n = self.pin.pin() as usize;
r.cr(n / 8).modify(|w| w.set_mode(n % 8, speed.to_mode())); r.cr(n / 8).modify(|w| w.set_mode(n % 8, speed.to_mode()));
r.cr(n / 8).modify(|w| w.set_cnf_out(n % 8, vals::CnfOut::OPENDRAIN)); r.cr(n / 8).modify(|w| w.set_cnf_out(n % 8, vals::CnfOut::OPEN_DRAIN));
}); });
#[cfg(gpio_v2)] #[cfg(gpio_v2)]
@ -130,7 +130,7 @@ impl<'d> Flex<'d> {
let r = self.pin.block(); let r = self.pin.block();
let n = self.pin.pin() as usize; let n = self.pin.pin() as usize;
r.pupdr().modify(|w| w.set_pupdr(n, pull.to_pupdr())); r.pupdr().modify(|w| w.set_pupdr(n, pull.to_pupdr()));
r.otyper().modify(|w| w.set_ot(n, vals::Ot::OPENDRAIN)); r.otyper().modify(|w| w.set_ot(n, vals::Ot::OPEN_DRAIN));
r.ospeedr().modify(|w| w.set_ospeedr(n, speed.to_ospeedr())); r.ospeedr().modify(|w| w.set_ospeedr(n, speed.to_ospeedr()));
r.moder().modify(|w| w.set_moder(n, vals::Moder::OUTPUT)); r.moder().modify(|w| w.set_moder(n, vals::Moder::OUTPUT));
}); });
@ -253,8 +253,8 @@ impl Pull {
const fn to_pupdr(self) -> vals::Pupdr { const fn to_pupdr(self) -> vals::Pupdr {
match self { match self {
Pull::None => vals::Pupdr::FLOATING, Pull::None => vals::Pupdr::FLOATING,
Pull::Up => vals::Pupdr::PULLUP, Pull::Up => vals::Pupdr::PULL_UP,
Pull::Down => vals::Pupdr::PULLDOWN, Pull::Down => vals::Pupdr::PULL_DOWN,
} }
} }
} }
@ -293,11 +293,11 @@ impl Speed {
#[cfg(gpio_v2)] #[cfg(gpio_v2)]
const fn to_ospeedr(self: Speed) -> vals::Ospeedr { const fn to_ospeedr(self: Speed) -> vals::Ospeedr {
match self { match self {
Speed::Low => vals::Ospeedr::LOWSPEED, Speed::Low => vals::Ospeedr::LOW_SPEED,
Speed::Medium => vals::Ospeedr::MEDIUMSPEED, Speed::Medium => vals::Ospeedr::MEDIUM_SPEED,
#[cfg(not(syscfg_f0))] #[cfg(not(syscfg_f0))]
Speed::High => vals::Ospeedr::HIGHSPEED, Speed::High => vals::Ospeedr::HIGH_SPEED,
Speed::VeryHigh => vals::Ospeedr::VERYHIGHSPEED, Speed::VeryHigh => vals::Ospeedr::VERY_HIGH_SPEED,
} }
} }
} }
@ -539,16 +539,16 @@ impl OutputType {
#[cfg(gpio_v1)] #[cfg(gpio_v1)]
const fn to_cnf_out(self) -> vals::CnfOut { const fn to_cnf_out(self) -> vals::CnfOut {
match self { match self {
OutputType::PushPull => vals::CnfOut::ALTPUSHPULL, OutputType::PushPull => vals::CnfOut::ALT_PUSH_PULL,
OutputType::OpenDrain => vals::CnfOut::ALTOPENDRAIN, OutputType::OpenDrain => vals::CnfOut::ALT_OPEN_DRAIN,
} }
} }
#[cfg(gpio_v2)] #[cfg(gpio_v2)]
const fn to_ot(self) -> vals::Ot { const fn to_ot(self) -> vals::Ot {
match self { match self {
OutputType::PushPull => vals::Ot::PUSHPULL, OutputType::PushPull => vals::Ot::PUSH_PULL,
OutputType::OpenDrain => vals::Ot::OPENDRAIN, OutputType::OpenDrain => vals::Ot::OPEN_DRAIN,
} }
} }
} }
@ -624,8 +624,8 @@ impl AfType {
pub const fn input(pull: Pull) -> Self { pub const fn input(pull: Pull) -> Self {
Self { Self {
pupdr: pull.to_pupdr(), pupdr: pull.to_pupdr(),
ot: vals::Ot::PUSHPULL, ot: vals::Ot::PUSH_PULL,
ospeedr: vals::Ospeedr::LOWSPEED, ospeedr: vals::Ospeedr::LOW_SPEED,
} }
} }
@ -705,8 +705,8 @@ fn get_pull(pin_port: u8) -> Pull {
#[cfg(gpio_v2)] #[cfg(gpio_v2)]
return match r.pupdr().read().pupdr(n) { return match r.pupdr().read().pupdr(n) {
vals::Pupdr::FLOATING => Pull::None, vals::Pupdr::FLOATING => Pull::None,
vals::Pupdr::PULLDOWN => Pull::Down, vals::Pupdr::PULL_DOWN => Pull::Down,
vals::Pupdr::PULLUP => Pull::Up, vals::Pupdr::PULL_UP => Pull::Up,
vals::Pupdr::_RESERVED_3 => Pull::None, vals::Pupdr::_RESERVED_3 => Pull::None,
}; };
} }

6
embassy-stm32/src/i2c/v2.rs
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@ -74,7 +74,7 @@ impl<'d, M: Mode> I2c<'d, M> {
// is BUSY or I2C is in slave mode. // is BUSY or I2C is in slave mode.
let reload = if reload { let reload = if reload {
i2c::vals::Reload::NOTCOMPLETED i2c::vals::Reload::NOT_COMPLETED
} else { } else {
i2c::vals::Reload::COMPLETED i2c::vals::Reload::COMPLETED
}; };
@ -115,7 +115,7 @@ impl<'d, M: Mode> I2c<'d, M> {
} }
let reload = if reload { let reload = if reload {
i2c::vals::Reload::NOTCOMPLETED i2c::vals::Reload::NOT_COMPLETED
} else { } else {
i2c::vals::Reload::COMPLETED i2c::vals::Reload::COMPLETED
}; };
@ -144,7 +144,7 @@ impl<'d, M: Mode> I2c<'d, M> {
} }
let reload = if reload { let reload = if reload {
i2c::vals::Reload::NOTCOMPLETED i2c::vals::Reload::NOT_COMPLETED
} else { } else {
i2c::vals::Reload::COMPLETED i2c::vals::Reload::COMPLETED
}; };

16
embassy-stm32/src/i2s.rs
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@ -141,8 +141,8 @@ impl ClockPolarity {
#[cfg(any(spi_v1, spi_v3, spi_f1))] #[cfg(any(spi_v1, spi_v3, spi_f1))]
const fn ckpol(&self) -> vals::Ckpol { const fn ckpol(&self) -> vals::Ckpol {
match self { match self {
ClockPolarity::IdleHigh => vals::Ckpol::IDLEHIGH, ClockPolarity::IdleHigh => vals::Ckpol::IDLE_HIGH,
ClockPolarity::IdleLow => vals::Ckpol::IDLELOW, ClockPolarity::IdleLow => vals::Ckpol::IDLE_LOW,
} }
} }
} }
@ -564,14 +564,14 @@ impl<'d, W: Word> I2S<'d, W> {
w.set_chlen(config.format.chlen()); w.set_chlen(config.format.chlen());
w.set_i2scfg(match (config.mode, function) { w.set_i2scfg(match (config.mode, function) {
(Mode::Master, Function::Transmit) => I2scfg::MASTERTX, (Mode::Master, Function::Transmit) => I2scfg::MASTER_TX,
(Mode::Master, Function::Receive) => I2scfg::MASTERRX, (Mode::Master, Function::Receive) => I2scfg::MASTER_RX,
#[cfg(spi_v3)] #[cfg(spi_v3)]
(Mode::Master, Function::FullDuplex) => I2scfg::MASTERFULLDUPLEX, (Mode::Master, Function::FullDuplex) => I2scfg::MASTER_FULL_DUPLEX,
(Mode::Slave, Function::Transmit) => I2scfg::SLAVETX, (Mode::Slave, Function::Transmit) => I2scfg::SLAVE_TX,
(Mode::Slave, Function::Receive) => I2scfg::SLAVERX, (Mode::Slave, Function::Receive) => I2scfg::SLAVE_RX,
#[cfg(spi_v3)] #[cfg(spi_v3)]
(Mode::Slave, Function::FullDuplex) => I2scfg::SLAVEFULLDUPLEX, (Mode::Slave, Function::FullDuplex) => I2scfg::SLAVE_FULL_DUPLEX,
}); });
#[cfg(any(spi_v1, spi_f1))] #[cfg(any(spi_v1, spi_f1))]

4
embassy-stm32/src/lptim/timer/channel_direction.rs
View File

@ -11,8 +11,8 @@ pub enum ChannelDirection {
impl From<ChannelDirection> for vals::Ccsel { impl From<ChannelDirection> for vals::Ccsel {
fn from(direction: ChannelDirection) -> Self { fn from(direction: ChannelDirection) -> Self {
match direction { match direction {
ChannelDirection::OutputPwm => vals::Ccsel::OUTPUTCOMPARE, ChannelDirection::OutputPwm => vals::Ccsel::OUTPUT_COMPARE,
ChannelDirection::InputCapture => vals::Ccsel::INPUTCAPTURE, ChannelDirection::InputCapture => vals::Ccsel::INPUT_CAPTURE,
} }
} }
} }

16
embassy-stm32/src/ltdc.rs
View File

@ -261,23 +261,23 @@ impl<'d, T: Instance> Ltdc<'d, T> {
// configure the HS, VS, DE and PC polarity // configure the HS, VS, DE and PC polarity
ltdc.gcr().modify(|w| { ltdc.gcr().modify(|w| {
w.set_hspol(match config.h_sync_polarity { w.set_hspol(match config.h_sync_polarity {
PolarityActive::ActiveHigh => Hspol::ACTIVEHIGH, PolarityActive::ActiveHigh => Hspol::ACTIVE_HIGH,
PolarityActive::ActiveLow => Hspol::ACTIVELOW, PolarityActive::ActiveLow => Hspol::ACTIVE_LOW,
}); });
w.set_vspol(match config.v_sync_polarity { w.set_vspol(match config.v_sync_polarity {
PolarityActive::ActiveHigh => Vspol::ACTIVEHIGH, PolarityActive::ActiveHigh => Vspol::ACTIVE_HIGH,
PolarityActive::ActiveLow => Vspol::ACTIVELOW, PolarityActive::ActiveLow => Vspol::ACTIVE_LOW,
}); });
w.set_depol(match config.data_enable_polarity { w.set_depol(match config.data_enable_polarity {
PolarityActive::ActiveHigh => Depol::ACTIVEHIGH, PolarityActive::ActiveHigh => Depol::ACTIVE_HIGH,
PolarityActive::ActiveLow => Depol::ACTIVELOW, PolarityActive::ActiveLow => Depol::ACTIVE_LOW,
}); });
w.set_pcpol(match config.pixel_clock_polarity { w.set_pcpol(match config.pixel_clock_polarity {
PolarityEdge::RisingEdge => Pcpol::RISINGEDGE, PolarityEdge::RisingEdge => Pcpol::RISING_EDGE,
PolarityEdge::FallingEdge => Pcpol::FALLINGEDGE, PolarityEdge::FallingEdge => Pcpol::FALLING_EDGE,
}); });
}); });

6
embassy-stm32/src/opamp.rs
View File

@ -30,7 +30,7 @@ impl From<OpAmpSpeed> for crate::pac::opamp::vals::Opahsm {
fn from(v: OpAmpSpeed) -> Self { fn from(v: OpAmpSpeed) -> Self {
match v { match v {
OpAmpSpeed::Normal => crate::pac::opamp::vals::Opahsm::NORMAL, OpAmpSpeed::Normal => crate::pac::opamp::vals::Opahsm::NORMAL,
OpAmpSpeed::HighSpeed => crate::pac::opamp::vals::Opahsm::HIGHSPEED, OpAmpSpeed::HighSpeed => crate::pac::opamp::vals::Opahsm::HIGH_SPEED,
} }
} }
} }
@ -105,7 +105,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
w.set_vm_sel(VmSel::from_bits(vm_sel)); w.set_vm_sel(VmSel::from_bits(vm_sel));
w.set_pga_gain(PgaGain::from_bits(pga_gain)); w.set_pga_gain(PgaGain::from_bits(pga_gain));
#[cfg(opamp_g4)] #[cfg(opamp_g4)]
w.set_opaintoen(Opaintoen::OUTPUTPIN); w.set_opaintoen(Opaintoen::OUTPUT_PIN);
w.set_opampen(true); w.set_opampen(true);
}); });
@ -131,7 +131,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
w.set_vm_sel(VmSel::OUTPUT); w.set_vm_sel(VmSel::OUTPUT);
w.set_vp_sel(VpSel::DAC3_CH1); w.set_vp_sel(VpSel::DAC3_CH1);
w.set_opaintoen(Opaintoen::OUTPUTPIN); w.set_opaintoen(Opaintoen::OUTPUT_PIN);
w.set_opampen(true); w.set_opampen(true);
}); });

26
embassy-stm32/src/ospi/mod.rs
View File

@ -218,7 +218,7 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
// Enable memory mapped mode // Enable memory mapped mode
reg.cr().modify(|r| { reg.cr().modify(|r| {
r.set_fmode(crate::ospi::vals::FunctionalMode::MEMORYMAPPED); r.set_fmode(crate::ospi::vals::FunctionalMode::MEMORY_MAPPED);
r.set_tcen(false); r.set_tcen(false);
}); });
Ok(()) Ok(())
@ -229,7 +229,7 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
let reg = T::REGS; let reg = T::REGS;
reg.cr().modify(|r| { reg.cr().modify(|r| {
r.set_fmode(crate::ospi::vals::FunctionalMode::INDIRECTWRITE); r.set_fmode(crate::ospi::vals::FunctionalMode::INDIRECT_WRITE);
r.set_abort(true); r.set_abort(true);
r.set_dmaen(false); r.set_dmaen(false);
r.set_en(false); r.set_en(false);
@ -388,7 +388,7 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
T::REGS.tcr().modify(|w| { T::REGS.tcr().modify(|w| {
w.set_sshift(match config.sample_shifting { w.set_sshift(match config.sample_shifting {
true => vals::SampleShift::HALFCYCLE, true => vals::SampleShift::HALF_CYCLE,
false => vals::SampleShift::NONE, false => vals::SampleShift::NONE,
}); });
w.set_dhqc(config.delay_hold_quarter_cycle); w.set_dhqc(config.delay_hold_quarter_cycle);
@ -556,7 +556,9 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
let current_instruction = T::REGS.ir().read().instruction(); let current_instruction = T::REGS.ir().read().instruction();
// For a indirect read transaction, the transaction begins when the instruction/address is set // For a indirect read transaction, the transaction begins when the instruction/address is set
T::REGS.cr().modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECTREAD)); T::REGS
.cr()
.modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECT_READ));
if T::REGS.ccr().read().admode() == vals::PhaseMode::NONE { if T::REGS.ccr().read().admode() == vals::PhaseMode::NONE {
T::REGS.ir().write(|v| v.set_instruction(current_instruction)); T::REGS.ir().write(|v| v.set_instruction(current_instruction));
} else { } else {
@ -591,7 +593,7 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
T::REGS T::REGS
.cr() .cr()
.modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECTWRITE)); .modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECT_WRITE));
for idx in 0..buf.len() { for idx in 0..buf.len() {
while !T::REGS.sr().read().ftf() {} while !T::REGS.sr().read().ftf() {}
@ -653,7 +655,7 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
T::REGS.tcr().modify(|w| { T::REGS.tcr().modify(|w| {
w.set_sshift(match config.sample_shifting { w.set_sshift(match config.sample_shifting {
true => vals::SampleShift::HALFCYCLE, true => vals::SampleShift::HALF_CYCLE,
false => vals::SampleShift::NONE, false => vals::SampleShift::NONE,
}); });
w.set_dhqc(config.delay_hold_quarter_cycle); w.set_dhqc(config.delay_hold_quarter_cycle);
@ -1051,7 +1053,9 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
let current_instruction = T::REGS.ir().read().instruction(); let current_instruction = T::REGS.ir().read().instruction();
// For a indirect read transaction, the transaction begins when the instruction/address is set // For a indirect read transaction, the transaction begins when the instruction/address is set
T::REGS.cr().modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECTREAD)); T::REGS
.cr()
.modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECT_READ));
if T::REGS.ccr().read().admode() == vals::PhaseMode::NONE { if T::REGS.ccr().read().admode() == vals::PhaseMode::NONE {
T::REGS.ir().write(|v| v.set_instruction(current_instruction)); T::REGS.ir().write(|v| v.set_instruction(current_instruction));
} else { } else {
@ -1086,7 +1090,7 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
self.configure_command(&transaction, Some(buf.len()))?; self.configure_command(&transaction, Some(buf.len()))?;
T::REGS T::REGS
.cr() .cr()
.modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECTWRITE)); .modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECT_WRITE));
let transfer = unsafe { let transfer = unsafe {
self.dma self.dma
@ -1119,7 +1123,9 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
let current_instruction = T::REGS.ir().read().instruction(); let current_instruction = T::REGS.ir().read().instruction();
// For a indirect read transaction, the transaction begins when the instruction/address is set // For a indirect read transaction, the transaction begins when the instruction/address is set
T::REGS.cr().modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECTREAD)); T::REGS
.cr()
.modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECT_READ));
if T::REGS.ccr().read().admode() == vals::PhaseMode::NONE { if T::REGS.ccr().read().admode() == vals::PhaseMode::NONE {
T::REGS.ir().write(|v| v.set_instruction(current_instruction)); T::REGS.ir().write(|v| v.set_instruction(current_instruction));
} else { } else {
@ -1154,7 +1160,7 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
self.configure_command(&transaction, Some(buf.len()))?; self.configure_command(&transaction, Some(buf.len()))?;
T::REGS T::REGS
.cr() .cr()
.modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECTWRITE)); .modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECT_WRITE));
let transfer = unsafe { let transfer = unsafe {
self.dma self.dma

4
embassy-stm32/src/rcc/bd.rs
View File

@ -45,8 +45,8 @@ impl From<LseDrive> for crate::pac::rcc::vals::Lsedrv {
match value { match value {
#[cfg(not(stm32h5))] // ES0565: LSE Low drive mode is not functional #[cfg(not(stm32h5))] // ES0565: LSE Low drive mode is not functional
LseDrive::Low => Lsedrv::LOW, LseDrive::Low => Lsedrv::LOW,
LseDrive::MediumLow => Lsedrv::MEDIUMLOW, LseDrive::MediumLow => Lsedrv::MEDIUM_LOW,
LseDrive::MediumHigh => Lsedrv::MEDIUMHIGH, LseDrive::MediumHigh => Lsedrv::MEDIUM_HIGH,
LseDrive::High => Lsedrv::HIGH, LseDrive::High => Lsedrv::HIGH,
} }
} }

12
embassy-stm32/src/rcc/f013.rs
View File

@ -332,9 +332,9 @@ pub(crate) unsafe fn init(config: Config) {
assert!(!(adcpres == AdcHclkPrescaler::Div1 && config.ahb_pre != AHBPrescaler::DIV1)); assert!(!(adcpres == AdcHclkPrescaler::Div1 && config.ahb_pre != AHBPrescaler::DIV1));
let (div, ckmode) = match adcpres { let (div, ckmode) = match adcpres {
AdcHclkPrescaler::Div1 => (1u32, Ckmode::SYNCDIV1), AdcHclkPrescaler::Div1 => (1u32, Ckmode::SYNC_DIV1),
AdcHclkPrescaler::Div2 => (2u32, Ckmode::SYNCDIV2), AdcHclkPrescaler::Div2 => (2u32, Ckmode::SYNC_DIV2),
AdcHclkPrescaler::Div4 => (4u32, Ckmode::SYNCDIV4), AdcHclkPrescaler::Div4 => (4u32, Ckmode::SYNC_DIV4),
}; };
common.ccr().modify(|w| w.set_ckmode(ckmode)); common.ccr().modify(|w| w.set_ckmode(ckmode));
@ -361,9 +361,9 @@ pub(crate) unsafe fn init(config: Config) {
assert!(!(adcpres == AdcHclkPrescaler::Div1 && config.ahb_pre != AHBPrescaler::DIV1)); assert!(!(adcpres == AdcHclkPrescaler::Div1 && config.ahb_pre != AHBPrescaler::DIV1));
let (div, ckmode) = match adcpres { let (div, ckmode) = match adcpres {
AdcHclkPrescaler::Div1 => (1u32, Ckmode::SYNCDIV1), AdcHclkPrescaler::Div1 => (1u32, Ckmode::SYNC_DIV1),
AdcHclkPrescaler::Div2 => (2u32, Ckmode::SYNCDIV2), AdcHclkPrescaler::Div2 => (2u32, Ckmode::SYNC_DIV2),
AdcHclkPrescaler::Div4 => (4u32, Ckmode::SYNCDIV4), AdcHclkPrescaler::Div4 => (4u32, Ckmode::SYNC_DIV4),
}; };
common.ccr().modify(|w| w.set_ckmode(ckmode)); common.ccr().modify(|w| w.set_ckmode(ckmode));

8
embassy-stm32/src/rcc/h.rs
View File

@ -113,8 +113,8 @@ pub enum TimerPrescaler {
impl From<TimerPrescaler> for Timpre { impl From<TimerPrescaler> for Timpre {
fn from(value: TimerPrescaler) -> Self { fn from(value: TimerPrescaler) -> Self {
match value { match value {
TimerPrescaler::DefaultX2 => Timpre::DEFAULTX2, TimerPrescaler::DefaultX2 => Timpre::DEFAULT_X2,
TimerPrescaler::DefaultX4 => Timpre::DEFAULTX4, TimerPrescaler::DefaultX4 => Timpre::DEFAULT_X4,
} }
} }
} }
@ -788,9 +788,9 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
let vco_clk = ref_clk * config.mul; let vco_clk = ref_clk * config.mul;
let vco_range = if VCO_RANGE.contains(&vco_clk) { let vco_range = if VCO_RANGE.contains(&vco_clk) {
Pllvcosel::MEDIUMVCO Pllvcosel::MEDIUM_VCO
} else if wide_allowed && VCO_WIDE_RANGE.contains(&vco_clk) { } else if wide_allowed && VCO_WIDE_RANGE.contains(&vco_clk) {
Pllvcosel::WIDEVCO Pllvcosel::WIDE_VCO
} else { } else {
panic!("pll vco_clk out of range: {} hz", vco_clk.0) panic!("pll vco_clk out of range: {} hz", vco_clk.0)
}; };

8
embassy-stm32/src/rng.rs
View File

@ -88,10 +88,10 @@ impl<'d, T: Instance> Rng<'d, T> {
reg.set_nistc(pac::rng::vals::Nistc::CUSTOM); reg.set_nistc(pac::rng::vals::Nistc::CUSTOM);
// set RNG config "A" according to reference manual // set RNG config "A" according to reference manual
// this has to be written within the same write access as setting the CONDRST bit // this has to be written within the same write access as setting the CONDRST bit
reg.set_rng_config1(pac::rng::vals::RngConfig1::CONFIGA); reg.set_rng_config1(pac::rng::vals::RngConfig1::CONFIG_A);
reg.set_clkdiv(pac::rng::vals::Clkdiv::NODIV); reg.set_clkdiv(pac::rng::vals::Clkdiv::NO_DIV);
reg.set_rng_config2(pac::rng::vals::RngConfig2::CONFIGA_B); reg.set_rng_config2(pac::rng::vals::RngConfig2::CONFIG_A_B);
reg.set_rng_config3(pac::rng::vals::RngConfig3::CONFIGA); reg.set_rng_config3(pac::rng::vals::RngConfig3::CONFIG_A);
reg.set_ced(true); reg.set_ced(true);
reg.set_ie(false); reg.set_ie(false);
reg.set_rngen(true); reg.set_rngen(true);

4
embassy-stm32/src/rtc/v2.rs
View File

@ -77,7 +77,7 @@ impl super::Rtc {
// When the offset is positive (0 to 512), the opposite of // When the offset is positive (0 to 512), the opposite of
// the offset (512 - offset) is masked, i.e. for the // the offset (512 - offset) is masked, i.e. for the
// maximum offset (512), 0 pulses are masked. // maximum offset (512), 0 pulses are masked.
w.set_calp(stm32_metapac::rtc::vals::Calp::INCREASEFREQ); w.set_calp(stm32_metapac::rtc::vals::Calp::INCREASE_FREQ);
w.set_calm(512 - clock_drift as u16); w.set_calm(512 - clock_drift as u16);
} else { } else {
// Minimum (about -510.7) rounds to -511. // Minimum (about -510.7) rounds to -511.
@ -86,7 +86,7 @@ impl super::Rtc {
// When the offset is negative or zero (-511 to 0), // When the offset is negative or zero (-511 to 0),
// the absolute offset is masked, i.e. for the minimum // the absolute offset is masked, i.e. for the minimum
// offset (-511), 511 pulses are masked. // offset (-511), 511 pulses are masked.
w.set_calp(stm32_metapac::rtc::vals::Calp::NOCHANGE); w.set_calp(stm32_metapac::rtc::vals::Calp::NO_CHANGE);
w.set_calm((clock_drift * -1.0) as u16); w.set_calm((clock_drift * -1.0) as u16);
} }
}); });

12
embassy-stm32/src/rtc/v3.rs
View File

@ -12,7 +12,7 @@ impl super::Rtc {
self.write(true, |rtc| { self.write(true, |rtc| {
rtc.cr().modify(|w| { rtc.cr().modify(|w| {
w.set_bypshad(true); w.set_bypshad(true);
w.set_fmt(Fmt::TWENTYFOURHOUR); w.set_fmt(Fmt::TWENTY_FOUR_HOUR);
w.set_osel(Osel::DISABLED); w.set_osel(Osel::DISABLED);
w.set_pol(Pol::HIGH); w.set_pol(Pol::HIGH);
}); });
@ -25,7 +25,7 @@ impl super::Rtc {
// TODO: configuration for output pins // TODO: configuration for output pins
rtc.cr().modify(|w| { rtc.cr().modify(|w| {
w.set_out2en(false); w.set_out2en(false);
w.set_tampalrm_type(TampalrmType::PUSHPULL); w.set_tampalrm_type(TampalrmType::PUSH_PULL);
w.set_tampalrm_pu(false); w.set_tampalrm_pu(false);
}); });
}); });
@ -56,10 +56,10 @@ impl super::Rtc {
rtc.calr().write(|w| { rtc.calr().write(|w| {
match period { match period {
RtcCalibrationCyclePeriod::Seconds8 => { RtcCalibrationCyclePeriod::Seconds8 => {
w.set_calw8(Calw8::EIGHTSECONDS); w.set_calw8(Calw8::EIGHT_SECONDS);
} }
RtcCalibrationCyclePeriod::Seconds16 => { RtcCalibrationCyclePeriod::Seconds16 => {
w.set_calw16(Calw16::SIXTEENSECONDS); w.set_calw16(Calw16::SIXTEEN_SECONDS);
} }
RtcCalibrationCyclePeriod::Seconds32 => { RtcCalibrationCyclePeriod::Seconds32 => {
// Set neither `calw8` nor `calw16` to use 32 seconds // Set neither `calw8` nor `calw16` to use 32 seconds
@ -79,7 +79,7 @@ impl super::Rtc {
// When the offset is positive (0 to 512), the opposite of // When the offset is positive (0 to 512), the opposite of
// the offset (512 - offset) is masked, i.e. for the // the offset (512 - offset) is masked, i.e. for the
// maximum offset (512), 0 pulses are masked. // maximum offset (512), 0 pulses are masked.
w.set_calp(Calp::INCREASEFREQ); w.set_calp(Calp::INCREASE_FREQ);
w.set_calm(512 - clock_drift as u16); w.set_calm(512 - clock_drift as u16);
} else { } else {
// Minimum (about -510.7) rounds to -511. // Minimum (about -510.7) rounds to -511.
@ -88,7 +88,7 @@ impl super::Rtc {
// When the offset is negative or zero (-511 to 0), // When the offset is negative or zero (-511 to 0),
// the absolute offset is masked, i.e. for the minimum // the absolute offset is masked, i.e. for the minimum
// offset (-511), 511 pulses are masked. // offset (-511), 511 pulses are masked.
w.set_calp(Calp::NOCHANGE); w.set_calp(Calp::NO_CHANGE);
w.set_calm((clock_drift * -1.0) as u16); w.set_calm((clock_drift * -1.0) as u16);
} }
}); });

44
embassy-stm32/src/sai/mod.rs
View File

@ -52,12 +52,12 @@ impl Mode {
const fn mode(&self, tx_rx: TxRx) -> vals::Mode { const fn mode(&self, tx_rx: TxRx) -> vals::Mode {
match tx_rx { match tx_rx {
TxRx::Transmitter => match self { TxRx::Transmitter => match self {
Mode::Master => vals::Mode::MASTERTX, Mode::Master => vals::Mode::MASTER_TX,
Mode::Slave => vals::Mode::SLAVETX, Mode::Slave => vals::Mode::SLAVE_TX,
}, },
TxRx::Receiver => match self { TxRx::Receiver => match self {
Mode::Master => vals::Mode::MASTERRX, Mode::Master => vals::Mode::MASTER_RX,
Mode::Slave => vals::Mode::SLAVERX, Mode::Slave => vals::Mode::SLAVE_RX,
}, },
} }
} }
@ -86,7 +86,7 @@ impl SlotSize {
#[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))] #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn slotsz(&self) -> vals::Slotsz { const fn slotsz(&self) -> vals::Slotsz {
match self { match self {
SlotSize::DataSize => vals::Slotsz::DATASIZE, SlotSize::DataSize => vals::Slotsz::DATA_SIZE,
SlotSize::Channel16 => vals::Slotsz::BIT16, SlotSize::Channel16 => vals::Slotsz::BIT16,
SlotSize::Channel32 => vals::Slotsz::BIT32, SlotSize::Channel32 => vals::Slotsz::BIT32,
} }
@ -155,8 +155,8 @@ impl MuteValue {
#[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))] #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn muteval(&self) -> vals::Muteval { const fn muteval(&self) -> vals::Muteval {
match self { match self {
MuteValue::Zero => vals::Muteval::SENDZERO, MuteValue::Zero => vals::Muteval::SEND_ZERO,
MuteValue::LastValue => vals::Muteval::SENDLAST, MuteValue::LastValue => vals::Muteval::SEND_LAST,
} }
} }
} }
@ -251,8 +251,8 @@ impl BitOrder {
#[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))] #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn lsbfirst(&self) -> vals::Lsbfirst { const fn lsbfirst(&self) -> vals::Lsbfirst {
match self { match self {
BitOrder::LsbFirst => vals::Lsbfirst::LSBFIRST, BitOrder::LsbFirst => vals::Lsbfirst::LSB_FIRST,
BitOrder::MsbFirst => vals::Lsbfirst::MSBFIRST, BitOrder::MsbFirst => vals::Lsbfirst::MSB_FIRST,
} }
} }
} }
@ -270,8 +270,8 @@ impl FrameSyncOffset {
#[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))] #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn fsoff(&self) -> vals::Fsoff { const fn fsoff(&self) -> vals::Fsoff {
match self { match self {
FrameSyncOffset::OnFirstBit => vals::Fsoff::ONFIRST, FrameSyncOffset::OnFirstBit => vals::Fsoff::ON_FIRST,
FrameSyncOffset::BeforeFirstBit => vals::Fsoff::BEFOREFIRST, FrameSyncOffset::BeforeFirstBit => vals::Fsoff::BEFORE_FIRST,
} }
} }
} }
@ -289,8 +289,8 @@ impl FrameSyncPolarity {
#[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))] #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn fspol(&self) -> vals::Fspol { const fn fspol(&self) -> vals::Fspol {
match self { match self {
FrameSyncPolarity::ActiveLow => vals::Fspol::FALLINGEDGE, FrameSyncPolarity::ActiveLow => vals::Fspol::FALLING_EDGE,
FrameSyncPolarity::ActiveHigh => vals::Fspol::RISINGEDGE, FrameSyncPolarity::ActiveHigh => vals::Fspol::RISING_EDGE,
} }
} }
} }
@ -325,8 +325,8 @@ impl ClockStrobe {
#[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))] #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn ckstr(&self) -> vals::Ckstr { const fn ckstr(&self) -> vals::Ckstr {
match self { match self {
ClockStrobe::Falling => vals::Ckstr::FALLINGEDGE, ClockStrobe::Falling => vals::Ckstr::FALLING_EDGE,
ClockStrobe::Rising => vals::Ckstr::RISINGEDGE, ClockStrobe::Rising => vals::Ckstr::RISING_EDGE,
} }
} }
} }
@ -343,8 +343,8 @@ impl ComplementFormat {
#[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))] #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn cpl(&self) -> vals::Cpl { const fn cpl(&self) -> vals::Cpl {
match self { match self {
ComplementFormat::OnesComplement => vals::Cpl::ONESCOMPLEMENT, ComplementFormat::OnesComplement => vals::Cpl::ONES_COMPLEMENT,
ComplementFormat::TwosComplement => vals::Cpl::TWOSCOMPLEMENT, ComplementFormat::TwosComplement => vals::Cpl::TWOS_COMPLEMENT,
} }
} }
} }
@ -362,8 +362,8 @@ impl Companding {
#[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))] #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn comp(&self) -> vals::Comp { const fn comp(&self) -> vals::Comp {
match self { match self {
Companding::None => vals::Comp::NOCOMPANDING, Companding::None => vals::Comp::NO_COMPANDING,
Companding::MuLaw => vals::Comp::MULAW, Companding::MuLaw => vals::Comp::MU_LAW,
Companding::ALaw => vals::Comp::ALAW, Companding::ALaw => vals::Comp::ALAW,
} }
} }
@ -381,7 +381,7 @@ impl OutputDrive {
#[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))] #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
const fn outdriv(&self) -> vals::Outdriv { const fn outdriv(&self) -> vals::Outdriv {
match self { match self {
OutputDrive::OnStart => vals::Outdriv::ONSTART, OutputDrive::OnStart => vals::Outdriv::ON_START,
OutputDrive::Immediately => vals::Outdriv::IMMEDIATELY, OutputDrive::Immediately => vals::Outdriv::IMMEDIATELY,
} }
} }
@ -907,9 +907,9 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
w.set_mckdiv(config.master_clock_divider.mckdiv()); w.set_mckdiv(config.master_clock_divider.mckdiv());
w.set_nodiv( w.set_nodiv(
if config.master_clock_divider == MasterClockDivider::MasterClockDisabled { if config.master_clock_divider == MasterClockDivider::MasterClockDisabled {
vals::Nodiv::NODIV vals::Nodiv::NO_DIV
} else { } else {
vals::Nodiv::MASTERCLOCK vals::Nodiv::MASTER_CLOCK
}, },
); );
w.set_dmaen(true); w.set_dmaen(true);

24
embassy-stm32/src/spi/mod.rs
View File

@ -75,15 +75,15 @@ impl Default for Config {
impl Config { impl Config {
fn raw_phase(&self) -> vals::Cpha { fn raw_phase(&self) -> vals::Cpha {
match self.mode.phase { match self.mode.phase {
Phase::CaptureOnSecondTransition => vals::Cpha::SECONDEDGE, Phase::CaptureOnSecondTransition => vals::Cpha::SECOND_EDGE,
Phase::CaptureOnFirstTransition => vals::Cpha::FIRSTEDGE, Phase::CaptureOnFirstTransition => vals::Cpha::FIRST_EDGE,
} }
} }
fn raw_polarity(&self) -> vals::Cpol { fn raw_polarity(&self) -> vals::Cpol {
match self.mode.polarity { match self.mode.polarity {
Polarity::IdleHigh => vals::Cpol::IDLEHIGH, Polarity::IdleHigh => vals::Cpol::IDLE_HIGH,
Polarity::IdleLow => vals::Cpol::IDLELOW, Polarity::IdleLow => vals::Cpol::IDLE_LOW,
} }
} }
@ -180,7 +180,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
// we're doing "fake rxonly", by actually writing one // we're doing "fake rxonly", by actually writing one
// byte to TXDR for each byte we want to receive. if we // byte to TXDR for each byte we want to receive. if we
// set OUTPUTDISABLED here, this hangs. // set OUTPUTDISABLED here, this hangs.
w.set_rxonly(vals::Rxonly::FULLDUPLEX); w.set_rxonly(vals::Rxonly::FULL_DUPLEX);
w.set_dff(<u8 as SealedWord>::CONFIG) w.set_dff(<u8 as SealedWord>::CONFIG)
}); });
} }
@ -217,18 +217,18 @@ impl<'d, M: PeriMode> Spi<'d, M> {
w.set_lsbfirst(lsbfirst); w.set_lsbfirst(lsbfirst);
w.set_ssm(true); w.set_ssm(true);
w.set_master(vals::Master::MASTER); w.set_master(vals::Master::MASTER);
w.set_comm(vals::Comm::FULLDUPLEX); w.set_comm(vals::Comm::FULL_DUPLEX);
w.set_ssom(vals::Ssom::ASSERTED); w.set_ssom(vals::Ssom::ASSERTED);
w.set_midi(0); w.set_midi(0);
w.set_mssi(0); w.set_mssi(0);
w.set_afcntr(true); w.set_afcntr(true);
w.set_ssiop(vals::Ssiop::ACTIVEHIGH); w.set_ssiop(vals::Ssiop::ACTIVE_HIGH);
}); });
regs.cfg1().modify(|w| { regs.cfg1().modify(|w| {
w.set_crcen(false); w.set_crcen(false);
w.set_mbr(br); w.set_mbr(br);
w.set_dsize(<u8 as SealedWord>::CONFIG); w.set_dsize(<u8 as SealedWord>::CONFIG);
w.set_fthlv(vals::Fthlv::ONEFRAME); w.set_fthlv(vals::Fthlv::ONE_FRAME);
}); });
regs.cr2().modify(|w| { regs.cr2().modify(|w| {
w.set_tsize(0); w.set_tsize(0);
@ -291,12 +291,12 @@ impl<'d, M: PeriMode> Spi<'d, M> {
#[cfg(any(spi_v3, spi_v4, spi_v5))] #[cfg(any(spi_v3, spi_v4, spi_v5))]
let cfg1 = self.info.regs.cfg1().read(); let cfg1 = self.info.regs.cfg1().read();
let polarity = if cfg.cpol() == vals::Cpol::IDLELOW { let polarity = if cfg.cpol() == vals::Cpol::IDLE_LOW {
Polarity::IdleLow Polarity::IdleLow
} else { } else {
Polarity::IdleHigh Polarity::IdleHigh
}; };
let phase = if cfg.cpha() == vals::Cpha::FIRSTEDGE { let phase = if cfg.cpha() == vals::Cpha::FIRST_EDGE {
Phase::CaptureOnFirstTransition Phase::CaptureOnFirstTransition
} else { } else {
Phase::CaptureOnSecondTransition Phase::CaptureOnSecondTransition
@ -693,8 +693,8 @@ impl<'d> Spi<'d, Async> {
w.i2smod().then(|| { w.i2smod().then(|| {
let prev = w.i2scfg(); let prev = w.i2scfg();
w.set_i2scfg(match prev { w.set_i2scfg(match prev {
vals::I2scfg::SLAVERX | vals::I2scfg::SLAVEFULLDUPLEX => vals::I2scfg::SLAVERX, vals::I2scfg::SLAVE_RX | vals::I2scfg::SLAVE_FULL_DUPLEX => vals::I2scfg::SLAVE_RX,
vals::I2scfg::MASTERRX | vals::I2scfg::MASTERFULLDUPLEX => vals::I2scfg::MASTERRX, vals::I2scfg::MASTER_RX | vals::I2scfg::MASTER_FULL_DUPLEX => vals::I2scfg::MASTER_RX,
_ => panic!("unsupported configuration"), _ => panic!("unsupported configuration"),
}); });
prev prev

4
embassy-stm32/src/time_driver.rs
View File

@ -246,9 +246,9 @@ impl RtcDriver {
r.arr().write(|w| w.set_arr(u16::MAX)); r.arr().write(|w| w.set_arr(u16::MAX));
// Set URS, generate update and clear URS // Set URS, generate update and clear URS
r.cr1().modify(|w| w.set_urs(vals::Urs::COUNTERONLY)); r.cr1().modify(|w| w.set_urs(vals::Urs::COUNTER_ONLY));
r.egr().write(|w| w.set_ug(true)); r.egr().write(|w| w.set_ug(true));
r.cr1().modify(|w| w.set_urs(vals::Urs::ANYEVENT)); r.cr1().modify(|w| w.set_urs(vals::Urs::ANY_EVENT));
// Mid-way point // Mid-way point
r.ccr(0).write(|w| w.set_ccr(0x8000)); r.ccr(0).write(|w| w.set_ccr(0x8000));

2
embassy-stm32/src/timer/input_capture.rs
View File

@ -129,7 +129,7 @@ impl<'d, T: GeneralInstance4Channel> InputCapture<'d, T> {
// Configuration steps from ST RM0390 (STM32F446) chapter 17.3.5 // Configuration steps from ST RM0390 (STM32F446) chapter 17.3.5
// or ST RM0008 (STM32F103) chapter 15.3.5 Input capture mode // or ST RM0008 (STM32F103) chapter 15.3.5 Input capture mode
self.inner.set_input_ti_selection(channel, tisel); self.inner.set_input_ti_selection(channel, tisel);
self.inner.set_input_capture_filter(channel, FilterValue::NOFILTER); self.inner.set_input_capture_filter(channel, FilterValue::NO_FILTER);
self.inner.set_input_capture_mode(channel, mode); self.inner.set_input_capture_mode(channel, mode);
self.inner.set_input_capture_prescaler(channel, 0); self.inner.set_input_capture_prescaler(channel, 0);
self.inner.enable_channel(channel, true); self.inner.enable_channel(channel, true);

40
embassy-stm32/src/timer/low_level.rs
View File

@ -95,11 +95,11 @@ impl CountingMode {
impl From<CountingMode> for (vals::Cms, vals::Dir) { impl From<CountingMode> for (vals::Cms, vals::Dir) {
fn from(value: CountingMode) -> Self { fn from(value: CountingMode) -> Self {
match value { match value {
CountingMode::EdgeAlignedUp => (vals::Cms::EDGEALIGNED, vals::Dir::UP), CountingMode::EdgeAlignedUp => (vals::Cms::EDGE_ALIGNED, vals::Dir::UP),
CountingMode::EdgeAlignedDown => (vals::Cms::EDGEALIGNED, vals::Dir::DOWN), CountingMode::EdgeAlignedDown => (vals::Cms::EDGE_ALIGNED, vals::Dir::DOWN),
CountingMode::CenterAlignedDownInterrupts => (vals::Cms::CENTERALIGNED1, vals::Dir::UP), CountingMode::CenterAlignedDownInterrupts => (vals::Cms::CENTER_ALIGNED1, vals::Dir::UP),
CountingMode::CenterAlignedUpInterrupts => (vals::Cms::CENTERALIGNED2, vals::Dir::UP), CountingMode::CenterAlignedUpInterrupts => (vals::Cms::CENTER_ALIGNED2, vals::Dir::UP),
CountingMode::CenterAlignedBothInterrupts => (vals::Cms::CENTERALIGNED3, vals::Dir::UP), CountingMode::CenterAlignedBothInterrupts => (vals::Cms::CENTER_ALIGNED3, vals::Dir::UP),
} }
} }
} }
@ -107,11 +107,11 @@ impl From<CountingMode> for (vals::Cms, vals::Dir) {
impl From<(vals::Cms, vals::Dir)> for CountingMode { impl From<(vals::Cms, vals::Dir)> for CountingMode {
fn from(value: (vals::Cms, vals::Dir)) -> Self { fn from(value: (vals::Cms, vals::Dir)) -> Self {
match value { match value {
(vals::Cms::EDGEALIGNED, vals::Dir::UP) => CountingMode::EdgeAlignedUp, (vals::Cms::EDGE_ALIGNED, vals::Dir::UP) => CountingMode::EdgeAlignedUp,
(vals::Cms::EDGEALIGNED, vals::Dir::DOWN) => CountingMode::EdgeAlignedDown, (vals::Cms::EDGE_ALIGNED, vals::Dir::DOWN) => CountingMode::EdgeAlignedDown,
(vals::Cms::CENTERALIGNED1, _) => CountingMode::CenterAlignedDownInterrupts, (vals::Cms::CENTER_ALIGNED1, _) => CountingMode::CenterAlignedDownInterrupts,
(vals::Cms::CENTERALIGNED2, _) => CountingMode::CenterAlignedUpInterrupts, (vals::Cms::CENTER_ALIGNED2, _) => CountingMode::CenterAlignedUpInterrupts,
(vals::Cms::CENTERALIGNED3, _) => CountingMode::CenterAlignedBothInterrupts, (vals::Cms::CENTER_ALIGNED3, _) => CountingMode::CenterAlignedBothInterrupts,
} }
} }
} }
@ -150,13 +150,13 @@ impl From<OutputCompareMode> for stm32_metapac::timer::vals::Ocm {
fn from(mode: OutputCompareMode) -> Self { fn from(mode: OutputCompareMode) -> Self {
match mode { match mode {
OutputCompareMode::Frozen => stm32_metapac::timer::vals::Ocm::FROZEN, OutputCompareMode::Frozen => stm32_metapac::timer::vals::Ocm::FROZEN,
OutputCompareMode::ActiveOnMatch => stm32_metapac::timer::vals::Ocm::ACTIVEONMATCH, OutputCompareMode::ActiveOnMatch => stm32_metapac::timer::vals::Ocm::ACTIVE_ON_MATCH,
OutputCompareMode::InactiveOnMatch => stm32_metapac::timer::vals::Ocm::INACTIVEONMATCH, OutputCompareMode::InactiveOnMatch => stm32_metapac::timer::vals::Ocm::INACTIVE_ON_MATCH,
OutputCompareMode::Toggle => stm32_metapac::timer::vals::Ocm::TOGGLE, OutputCompareMode::Toggle => stm32_metapac::timer::vals::Ocm::TOGGLE,
OutputCompareMode::ForceInactive => stm32_metapac::timer::vals::Ocm::FORCEINACTIVE, OutputCompareMode::ForceInactive => stm32_metapac::timer::vals::Ocm::FORCE_INACTIVE,
OutputCompareMode::ForceActive => stm32_metapac::timer::vals::Ocm::FORCEACTIVE, OutputCompareMode::ForceActive => stm32_metapac::timer::vals::Ocm::FORCE_ACTIVE,
OutputCompareMode::PwmMode1 => stm32_metapac::timer::vals::Ocm::PWMMODE1, OutputCompareMode::PwmMode1 => stm32_metapac::timer::vals::Ocm::PWM_MODE1,
OutputCompareMode::PwmMode2 => stm32_metapac::timer::vals::Ocm::PWMMODE2, OutputCompareMode::PwmMode2 => stm32_metapac::timer::vals::Ocm::PWM_MODE2,
} }
} }
} }
@ -271,9 +271,9 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
regs.psc().write_value(psc); regs.psc().write_value(psc);
regs.arr().write(|r| r.set_arr(arr)); regs.arr().write(|r| r.set_arr(arr));
regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTERONLY)); regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
regs.egr().write(|r| r.set_ug(true)); regs.egr().write(|r| r.set_ug(true));
regs.cr1().modify(|r| r.set_urs(vals::Urs::ANYEVENT)); regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
} }
#[cfg(not(stm32l0))] #[cfg(not(stm32l0))]
TimerBits::Bits32 => { TimerBits::Bits32 => {
@ -284,9 +284,9 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
regs.psc().write_value(psc); regs.psc().write_value(psc);
regs.arr().write_value(arr); regs.arr().write_value(arr);
regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTERONLY)); regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
regs.egr().write(|r| r.set_ug(true)); regs.egr().write(|r| r.set_ug(true));
regs.cr1().modify(|r| r.set_urs(vals::Urs::ANYEVENT)); regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
} }
} }
} }

8
embassy-stm32/src/timer/simple_pwm.rs
View File

@ -292,7 +292,7 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
/// Generate a sequence of PWM waveform /// Generate a sequence of PWM waveform
/// ///
/// Note: /// Note:
/// you will need to provide corresponding TIMx_UP DMA channel to use this method. /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
pub async fn waveform_up( pub async fn waveform_up(
&mut self, &mut self,
@ -377,12 +377,12 @@ macro_rules! impl_waveform_chx {
let original_duty_state = self.channel(cc_channel).current_duty_cycle(); let original_duty_state = self.channel(cc_channel).current_duty_cycle();
let original_enable_state = self.channel(cc_channel).is_enabled(); let original_enable_state = self.channel(cc_channel).is_enabled();
let original_cc_dma_on_update = self.inner.get_cc_dma_selection() == Ccds::ONUPDATE; let original_cc_dma_on_update = self.inner.get_cc_dma_selection() == Ccds::ON_UPDATE;
let original_cc_dma_enabled = self.inner.get_cc_dma_enable_state(cc_channel); let original_cc_dma_enabled = self.inner.get_cc_dma_enable_state(cc_channel);
// redirect CC DMA request onto Update Event // redirect CC DMA request onto Update Event
if !original_cc_dma_on_update { if !original_cc_dma_on_update {
self.inner.set_cc_dma_selection(Ccds::ONUPDATE) self.inner.set_cc_dma_selection(Ccds::ON_UPDATE)
} }
if !original_cc_dma_enabled { if !original_cc_dma_enabled {
@ -433,7 +433,7 @@ macro_rules! impl_waveform_chx {
} }
if !original_cc_dma_on_update { if !original_cc_dma_on_update {
self.inner.set_cc_dma_selection(Ccds::ONCOMPARE) self.inner.set_cc_dma_selection(Ccds::ON_COMPARE)
} }
} }
} }

10
embassy-stm32/src/ucpd.rs
View File

@ -484,11 +484,11 @@ impl<'d, T: Instance> PdPhy<'d, T> {
let sop = match r.rx_ordsetr().read().rxordset() { let sop = match r.rx_ordsetr().read().rxordset() {
Rxordset::SOP => Sop::Sop, Rxordset::SOP => Sop::Sop,
Rxordset::SOPPRIME => Sop::SopPrime, Rxordset::SOP_PRIME => Sop::SopPrime,
Rxordset::SOPDOUBLEPRIME => Sop::SopDoublePrime, Rxordset::SOP_DOUBLE_PRIME => Sop::SopDoublePrime,
Rxordset::SOPPRIMEDEBUG => Sop::SopPrimeDebug, Rxordset::SOP_PRIME_DEBUG => Sop::SopPrimeDebug,
Rxordset::SOPDOUBLEPRIMEDEBUG => Sop::SopDoublePrimeDebug, Rxordset::SOP_DOUBLE_PRIME_DEBUG => Sop::SopDoublePrimeDebug,
Rxordset::CABLERESET => return Err(RxError::HardReset), Rxordset::CABLE_RESET => return Err(RxError::HardReset),
// Extension headers are not supported // Extension headers are not supported
_ => unreachable!(), _ => unreachable!(),
}; };

14
examples/stm32f469/src/bin/dsi_bsp.rs
View File

@ -363,20 +363,20 @@ async fn main(_spawner: Spawner) {
const _PCPOLARITY: bool = false; // LTDC_PCPOLARITY_IPC == 0 const _PCPOLARITY: bool = false; // LTDC_PCPOLARITY_IPC == 0
const LTDC_DE_POLARITY: Depol = if !DE_POLARITY { const LTDC_DE_POLARITY: Depol = if !DE_POLARITY {
Depol::ACTIVELOW Depol::ACTIVE_LOW
} else { } else {
Depol::ACTIVEHIGH Depol::ACTIVE_HIGH
}; };
const LTDC_VS_POLARITY: Vspol = if !VS_POLARITY { const LTDC_VS_POLARITY: Vspol = if !VS_POLARITY {
Vspol::ACTIVEHIGH Vspol::ACTIVE_HIGH
} else { } else {
Vspol::ACTIVELOW Vspol::ACTIVE_LOW
}; };
const LTDC_HS_POLARITY: Hspol = if !HS_POLARITY { const LTDC_HS_POLARITY: Hspol = if !HS_POLARITY {
Hspol::ACTIVEHIGH Hspol::ACTIVE_HIGH
} else { } else {
Hspol::ACTIVELOW Hspol::ACTIVE_LOW
}; };
/* Timing Configuration */ /* Timing Configuration */
@ -397,7 +397,7 @@ async fn main(_spawner: Spawner) {
w.set_hspol(LTDC_HS_POLARITY); w.set_hspol(LTDC_HS_POLARITY);
w.set_vspol(LTDC_VS_POLARITY); w.set_vspol(LTDC_VS_POLARITY);
w.set_depol(LTDC_DE_POLARITY); w.set_depol(LTDC_DE_POLARITY);
w.set_pcpol(Pcpol::RISINGEDGE); w.set_pcpol(Pcpol::RISING_EDGE);
}); });
// Set Synchronization size // Set Synchronization size