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Consolidated hash drivers.

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This commit is contained in:
Caleb Garrett
2024-02-11 11:32:29 -05:00
parent 0c9661a661
commit eb64d71247
7 changed files with 565 additions and 823 deletions
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2
tests/stm32/Cargo.toml
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@@ -26,7 +26,7 @@ stm32l4a6zg = ["embassy-stm32/stm32l4a6zg", "chrono", "not-gpdma", "rng", "hash"
stm32l4r5zi = ["embassy-stm32/stm32l4r5zi", "chrono", "not-gpdma", "rng"]
stm32l552ze = ["embassy-stm32/stm32l552ze", "not-gpdma", "rng", "hash"]
stm32u585ai = ["embassy-stm32/stm32u585ai", "chrono", "rng", "hash"]
stm32u5a5zj = ["embassy-stm32/stm32u5a5zj", "chrono", "rng", "hash"]
stm32u5a5zj = ["embassy-stm32/stm32u5a5zj", "chrono", "rng"]
stm32wb55rg = ["embassy-stm32/stm32wb55rg", "chrono", "not-gpdma", "ble", "mac" , "rng"]
stm32wba52cg = ["embassy-stm32/stm32wba52cg", "chrono", "rng", "hash"]
stm32wl55jc = ["embassy-stm32/stm32wl55jc-cm4", "not-gpdma", "rng", "chrono"]

30
tests/stm32/src/bin/hash.rs
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@@ -6,6 +6,7 @@
mod common;
use common::*;
use embassy_executor::Spawner;
use embassy_stm32::dma::NoDma;
use embassy_stm32::hash::*;
use embassy_stm32::{bind_interrupts, hash, peripherals};
use sha2::{Digest, Sha224, Sha256};
@@ -30,27 +31,26 @@ bind_interrupts!(struct Irqs {
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let p: embassy_stm32::Peripherals = embassy_stm32::init(config());
let dma = peri!(p, HASH_DMA);
let mut hw_hasher = Hash::new(p.HASH, dma);
let mut hw_hasher = Hash::new(p.HASH, NoDma, Irqs);
let test_1: &[u8] = b"as;dfhaslfhas;oifvnasd;nifvnhasd;nifvhndlkfghsd;nvfnahssdfgsdafgsasdfasdfasdfasdfasdfghjklmnbvcalskdjghalskdjgfbaslkdjfgbalskdjgbalskdjbdfhsdfhsfghsfghfgh";
let test_2: &[u8] = b"fdhalksdjfhlasdjkfhalskdjfhgal;skdjfgalskdhfjgalskdjfglafgadfgdfgdafgaadsfgfgdfgadrgsyfthxfgjfhklhjkfgukhulkvhlvhukgfhfsrghzdhxyfufynufyuszeradrtydyytserr";
let test_3: &[u8] = b"a.ewtkluGWEBR.KAJRBTA,RMNRBG,FDMGB.kger.tkasjrbt.akrjtba.krjtba.ktmyna,nmbvtyliasd;gdrtba,sfvs.kgjzshd.gkbsr.tksejb.SDkfBSE.gkfgb>ESkfbSE>gkJSBESE>kbSE>fk";
// Start an SHA-256 digest.
let mut sha256context = hw_hasher.start(Algorithm::SHA256, DataType::Width8).await;
hw_hasher.update(&mut sha256context, test_1).await;
let mut sha256context = hw_hasher.start(Algorithm::SHA256, DataType::Width8);
hw_hasher.update_blocking(&mut sha256context, test_1);
// Interrupt the SHA-256 digest to compute an SHA-224 digest.
let mut sha224context = hw_hasher.start(Algorithm::SHA224, DataType::Width8).await;
hw_hasher.update(&mut sha224context, test_3).await;
let mut sha224_digest_buffer: [u8; 64] = [0; 64];
let sha224_digest = hw_hasher.finish(sha224context, &mut sha224_digest_buffer).await;
let mut sha224context = hw_hasher.start(Algorithm::SHA224, DataType::Width8);
hw_hasher.update_blocking(&mut sha224context, test_3);
let mut sha224_digest_buffer: [u8; 28] = [0; 28];
let _ = hw_hasher.finish_blocking(sha224context, &mut sha224_digest_buffer);
// Finish the SHA-256 digest.
hw_hasher.update(&mut sha256context, test_2).await;
let mut sha_256_digest_buffer: [u8; 64] = [0; 64];
let sha256_digest = hw_hasher.finish(sha256context, &mut sha_256_digest_buffer).await;
hw_hasher.update_blocking(&mut sha256context, test_2);
let mut sha256_digest_buffer: [u8; 32] = [0; 32];
let _ = hw_hasher.finish_blocking(sha256context, &mut sha256_digest_buffer);
// Compute the SHA-256 digest in software.
let mut sw_sha256_hasher = Sha256::new();
@@ -64,14 +64,14 @@ async fn main(_spawner: Spawner) {
let sw_sha224_digest = sw_sha224_hasher.finalize();
// Compare the SHA-256 digests.
info!("Hardware SHA-256 Digest: {:?}", sha256_digest);
info!("Hardware SHA-256 Digest: {:?}", sha256_digest_buffer);
info!("Software SHA-256 Digest: {:?}", sw_sha256_digest[..]);
defmt::assert!(*sha256_digest == sw_sha256_digest[..]);
defmt::assert!(sha256_digest_buffer == sw_sha256_digest[..]);
// Compare the SHA-224 digests.
info!("Hardware SHA-256 Digest: {:?}", sha224_digest);
info!("Hardware SHA-256 Digest: {:?}", sha224_digest_buffer);
info!("Software SHA-256 Digest: {:?}", sw_sha224_digest[..]);
defmt::assert!(*sha224_digest == sw_sha224_digest[..]);
defmt::assert!(sha224_digest_buffer == sw_sha224_digest[..]);
info!("Test OK");
cortex_m::asm::bkpt();

7
tests/stm32/src/common.rs
View File

@@ -128,7 +128,6 @@ define_peris!(
);
#[cfg(any(feature = "stm32h755zi", feature = "stm32h753zi"))]
define_peris!(
HASH_DMA = DMA1_CH0,
UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH0, UART_RX_DMA = DMA1_CH1,
SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PB5, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH0, SPI_RX_DMA = DMA1_CH1,
ADC = ADC1, DAC = DAC1, DAC_PIN = PA4,
@@ -142,21 +141,18 @@ define_peris!(
);
#[cfg(feature = "stm32u585ai")]
define_peris!(
HASH_DMA = GPDMA1_CH0,
UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
SPI = SPI1, SPI_SCK = PE13, SPI_MOSI = PE15, SPI_MISO = PE14, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
@irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
);
#[cfg(feature = "stm32u5a5zj")]
define_peris!(
HASH_DMA = GPDMA1_CH0,
UART = LPUART1, UART_TX = PG7, UART_RX = PG8, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
@irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
);
#[cfg(feature = "stm32h563zi")]
define_peris!(
HASH_DMA = GPDMA1_CH0,
UART = LPUART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
SPI = SPI4, SPI_SCK = PE12, SPI_MOSI = PE14, SPI_MISO = PE13, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
@irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
@@ -175,7 +171,6 @@ define_peris!(
);
#[cfg(feature = "stm32l4a6zg")]
define_peris!(
HASH_DMA = DMA2_CH7,
UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH2, UART_RX_DMA = DMA1_CH3,
SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
@irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
@@ -201,7 +196,6 @@ define_peris!(
);
#[cfg(feature = "stm32l552ze")]
define_peris!(
HASH_DMA = DMA1_CH1,
UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
@irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
@@ -232,7 +226,6 @@ define_peris!(
);
#[cfg(feature = "stm32wba52cg")]
define_peris!(
HASH_DMA = GPDMA1_CH0,
UART = LPUART1, UART_TX = PB5, UART_RX = PA10, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
SPI = SPI1, SPI_SCK = PB4, SPI_MOSI = PA15, SPI_MISO = PB3, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
@irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},