adding eeprom constants to _generated.rs
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@ -1922,6 +1922,47 @@ fn main() {
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pub const WRITE_SIZE: usize = #write_size;
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pub const WRITE_SIZE: usize = #write_size;
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));
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));
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// ========
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// Generate EEPROM constants
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let eeprom_memory_regions: Vec<&MemoryRegion> =
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memory.iter().filter(|x| x.kind == MemoryRegionKind::Eeprom).collect();
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if !eeprom_memory_regions.is_empty() {
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cfgs.enable("eeprom");
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cfgs.declare("eeprom");
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let mut sorted_eeprom_regions = eeprom_memory_regions.clone();
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sorted_eeprom_regions.sort_by_key(|r| r.address);
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let first_eeprom_address = sorted_eeprom_regions[0].address;
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let mut total_eeprom_size = 0;
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let mut current_expected_address = first_eeprom_address;
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for region in sorted_eeprom_regions.iter() {
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if region.address != current_expected_address {
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// For STM32L0 and STM32L1, EEPROM regions (if multiple) are expected to be contiguous.
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// If they are not, this indicates an issue with the chip metadata or an unsupported configuration.
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panic!(
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"EEPROM regions for chip {} are not contiguous, which is unexpected for L0/L1 series. \
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First region: '{}' at {:#X}. Found next non-contiguous region: '{}' at {:#X}. \
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Please verify chip metadata. Embassy currently assumes contiguous EEPROM for these series.",
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chip_name, sorted_eeprom_regions[0].name, first_eeprom_address, region.name, region.address
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);
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}
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total_eeprom_size += region.size;
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current_expected_address += region.size;
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}
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let eeprom_base_usize = first_eeprom_address as usize;
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let total_eeprom_size_usize = total_eeprom_size as usize;
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g.extend(quote! {
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pub const EEPROM_BASE: usize = #eeprom_base_usize;
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pub const EEPROM_SIZE: usize = #total_eeprom_size_usize;
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});
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}
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// ========
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// ========
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// Generate macro-tables
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// Generate macro-tables
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