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stm32f2 pll overflow with crystal

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With a large enough HSE input frequency, the vco clock calculation will
overflow a u32. Therefore, in this specific case we have to use the
inner value and cast to u64 to ensure the mul isn't clipped before
applying the divider.
This commit is contained in:
Scott Mabin 2023-07-30 01:00:50 +01:00
parent fcbfd224a7
commit e0ce7fcde7
1 changed files with 1 additions and 1 deletions
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2
embassy-stm32/src/rcc/f2.rs
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@ -58,7 +58,7 @@ impl Default for PLLConfig {
impl PLLConfig { impl PLLConfig {
pub fn clocks(&self, src_freq: Hertz) -> PLLClocks { pub fn clocks(&self, src_freq: Hertz) -> PLLClocks {
let in_freq = src_freq / self.pre_div; let in_freq = src_freq / self.pre_div;
let vco_freq = src_freq * self.mul / self.pre_div; let vco_freq = Hertz((src_freq.0 as u64 * self.mul.0 as u64 / self.pre_div.0 as u64) as u32);
let main_freq = vco_freq / self.main_div; let main_freq = vco_freq / self.main_div;
let pll48_freq = vco_freq / self.pll48_div; let pll48_freq = vco_freq / self.pll48_div;
PLLClocks { PLLClocks {