stm32: rename core features from _cmX to -cmX, cleanup gen.

ci.sh

@@ -28,7 +28,7 @@ cargo batch  \
     --- build --release --manifest-path embassy-nrf/Cargo.toml --target thumbv7em-none-eabi --features nrf52840,defmt \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f411ce,defmt \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32f429zi,log \
-    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h755zi_cm7,defmt \
+    --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32h755zi-cm7,defmt \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7em-none-eabi --features stm32l476vg,defmt \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv6m-none-eabi --features stm32l072cz,defmt \
     --- build --release --manifest-path embassy-stm32/Cargo.toml --target thumbv7m-none-eabi --features stm32l151cb-a,defmt \

embassy-stm32/Cargo.toml

@@ -615,40 +615,40 @@ stm32h743xg = [ "stm32-metapac/stm32h743xg" ]
 stm32h743xi = [ "stm32-metapac/stm32h743xi" ]
 stm32h743zg = [ "stm32-metapac/stm32h743zg" ]
 stm32h743zi = [ "stm32-metapac/stm32h743zi" ]
-stm32h745bg_cm7 = [ "stm32-metapac/stm32h745bg_cm7" ]
+stm32h745bg-cm7 = [ "stm32-metapac/stm32h745bg-cm7" ]
-stm32h745bg_cm4 = [ "stm32-metapac/stm32h745bg_cm4" ]
+stm32h745bg-cm4 = [ "stm32-metapac/stm32h745bg-cm4" ]
-stm32h745bi_cm7 = [ "stm32-metapac/stm32h745bi_cm7" ]
+stm32h745bi-cm7 = [ "stm32-metapac/stm32h745bi-cm7" ]
-stm32h745bi_cm4 = [ "stm32-metapac/stm32h745bi_cm4" ]
+stm32h745bi-cm4 = [ "stm32-metapac/stm32h745bi-cm4" ]
-stm32h745ig_cm7 = [ "stm32-metapac/stm32h745ig_cm7" ]
+stm32h745ig-cm7 = [ "stm32-metapac/stm32h745ig-cm7" ]
-stm32h745ig_cm4 = [ "stm32-metapac/stm32h745ig_cm4" ]
+stm32h745ig-cm4 = [ "stm32-metapac/stm32h745ig-cm4" ]
-stm32h745ii_cm7 = [ "stm32-metapac/stm32h745ii_cm7" ]
+stm32h745ii-cm7 = [ "stm32-metapac/stm32h745ii-cm7" ]
-stm32h745ii_cm4 = [ "stm32-metapac/stm32h745ii_cm4" ]
+stm32h745ii-cm4 = [ "stm32-metapac/stm32h745ii-cm4" ]
-stm32h745xg_cm7 = [ "stm32-metapac/stm32h745xg_cm7" ]
+stm32h745xg-cm7 = [ "stm32-metapac/stm32h745xg-cm7" ]
-stm32h745xg_cm4 = [ "stm32-metapac/stm32h745xg_cm4" ]
+stm32h745xg-cm4 = [ "stm32-metapac/stm32h745xg-cm4" ]
-stm32h745xi_cm7 = [ "stm32-metapac/stm32h745xi_cm7" ]
+stm32h745xi-cm7 = [ "stm32-metapac/stm32h745xi-cm7" ]
-stm32h745xi_cm4 = [ "stm32-metapac/stm32h745xi_cm4" ]
+stm32h745xi-cm4 = [ "stm32-metapac/stm32h745xi-cm4" ]
-stm32h745zg_cm7 = [ "stm32-metapac/stm32h745zg_cm7" ]
+stm32h745zg-cm7 = [ "stm32-metapac/stm32h745zg-cm7" ]
-stm32h745zg_cm4 = [ "stm32-metapac/stm32h745zg_cm4" ]
+stm32h745zg-cm4 = [ "stm32-metapac/stm32h745zg-cm4" ]
-stm32h745zi_cm7 = [ "stm32-metapac/stm32h745zi_cm7" ]
+stm32h745zi-cm7 = [ "stm32-metapac/stm32h745zi-cm7" ]
-stm32h745zi_cm4 = [ "stm32-metapac/stm32h745zi_cm4" ]
+stm32h745zi-cm4 = [ "stm32-metapac/stm32h745zi-cm4" ]
-stm32h747ag_cm7 = [ "stm32-metapac/stm32h747ag_cm7" ]
+stm32h747ag-cm7 = [ "stm32-metapac/stm32h747ag-cm7" ]
-stm32h747ag_cm4 = [ "stm32-metapac/stm32h747ag_cm4" ]
+stm32h747ag-cm4 = [ "stm32-metapac/stm32h747ag-cm4" ]
-stm32h747ai_cm7 = [ "stm32-metapac/stm32h747ai_cm7" ]
+stm32h747ai-cm7 = [ "stm32-metapac/stm32h747ai-cm7" ]
-stm32h747ai_cm4 = [ "stm32-metapac/stm32h747ai_cm4" ]
+stm32h747ai-cm4 = [ "stm32-metapac/stm32h747ai-cm4" ]
-stm32h747bg_cm7 = [ "stm32-metapac/stm32h747bg_cm7" ]
+stm32h747bg-cm7 = [ "stm32-metapac/stm32h747bg-cm7" ]
-stm32h747bg_cm4 = [ "stm32-metapac/stm32h747bg_cm4" ]
+stm32h747bg-cm4 = [ "stm32-metapac/stm32h747bg-cm4" ]
-stm32h747bi_cm7 = [ "stm32-metapac/stm32h747bi_cm7" ]
+stm32h747bi-cm7 = [ "stm32-metapac/stm32h747bi-cm7" ]
-stm32h747bi_cm4 = [ "stm32-metapac/stm32h747bi_cm4" ]
+stm32h747bi-cm4 = [ "stm32-metapac/stm32h747bi-cm4" ]
-stm32h747ig_cm7 = [ "stm32-metapac/stm32h747ig_cm7" ]
+stm32h747ig-cm7 = [ "stm32-metapac/stm32h747ig-cm7" ]
-stm32h747ig_cm4 = [ "stm32-metapac/stm32h747ig_cm4" ]
+stm32h747ig-cm4 = [ "stm32-metapac/stm32h747ig-cm4" ]
-stm32h747ii_cm7 = [ "stm32-metapac/stm32h747ii_cm7" ]
+stm32h747ii-cm7 = [ "stm32-metapac/stm32h747ii-cm7" ]
-stm32h747ii_cm4 = [ "stm32-metapac/stm32h747ii_cm4" ]
+stm32h747ii-cm4 = [ "stm32-metapac/stm32h747ii-cm4" ]
-stm32h747xg_cm7 = [ "stm32-metapac/stm32h747xg_cm7" ]
+stm32h747xg-cm7 = [ "stm32-metapac/stm32h747xg-cm7" ]
-stm32h747xg_cm4 = [ "stm32-metapac/stm32h747xg_cm4" ]
+stm32h747xg-cm4 = [ "stm32-metapac/stm32h747xg-cm4" ]
-stm32h747xi_cm7 = [ "stm32-metapac/stm32h747xi_cm7" ]
+stm32h747xi-cm7 = [ "stm32-metapac/stm32h747xi-cm7" ]
-stm32h747xi_cm4 = [ "stm32-metapac/stm32h747xi_cm4" ]
+stm32h747xi-cm4 = [ "stm32-metapac/stm32h747xi-cm4" ]
-stm32h747zi_cm7 = [ "stm32-metapac/stm32h747zi_cm7" ]
+stm32h747zi-cm7 = [ "stm32-metapac/stm32h747zi-cm7" ]
-stm32h747zi_cm4 = [ "stm32-metapac/stm32h747zi_cm4" ]
+stm32h747zi-cm4 = [ "stm32-metapac/stm32h747zi-cm4" ]
 stm32h750ib = [ "stm32-metapac/stm32h750ib" ]
 stm32h750vb = [ "stm32-metapac/stm32h750vb" ]
 stm32h750xb = [ "stm32-metapac/stm32h750xb" ]
@@ -659,24 +659,24 @@ stm32h753ii = [ "stm32-metapac/stm32h753ii" ]
 stm32h753vi = [ "stm32-metapac/stm32h753vi" ]
 stm32h753xi = [ "stm32-metapac/stm32h753xi" ]
 stm32h753zi = [ "stm32-metapac/stm32h753zi" ]
-stm32h755bi_cm7 = [ "stm32-metapac/stm32h755bi_cm7" ]
+stm32h755bi-cm7 = [ "stm32-metapac/stm32h755bi-cm7" ]
-stm32h755bi_cm4 = [ "stm32-metapac/stm32h755bi_cm4" ]
+stm32h755bi-cm4 = [ "stm32-metapac/stm32h755bi-cm4" ]
-stm32h755ii_cm7 = [ "stm32-metapac/stm32h755ii_cm7" ]
+stm32h755ii-cm7 = [ "stm32-metapac/stm32h755ii-cm7" ]
-stm32h755ii_cm4 = [ "stm32-metapac/stm32h755ii_cm4" ]
+stm32h755ii-cm4 = [ "stm32-metapac/stm32h755ii-cm4" ]
-stm32h755xi_cm7 = [ "stm32-metapac/stm32h755xi_cm7" ]
+stm32h755xi-cm7 = [ "stm32-metapac/stm32h755xi-cm7" ]
-stm32h755xi_cm4 = [ "stm32-metapac/stm32h755xi_cm4" ]
+stm32h755xi-cm4 = [ "stm32-metapac/stm32h755xi-cm4" ]
-stm32h755zi_cm7 = [ "stm32-metapac/stm32h755zi_cm7" ]
+stm32h755zi-cm7 = [ "stm32-metapac/stm32h755zi-cm7" ]
-stm32h755zi_cm4 = [ "stm32-metapac/stm32h755zi_cm4" ]
+stm32h755zi-cm4 = [ "stm32-metapac/stm32h755zi-cm4" ]
-stm32h757ai_cm7 = [ "stm32-metapac/stm32h757ai_cm7" ]
+stm32h757ai-cm7 = [ "stm32-metapac/stm32h757ai-cm7" ]
-stm32h757ai_cm4 = [ "stm32-metapac/stm32h757ai_cm4" ]
+stm32h757ai-cm4 = [ "stm32-metapac/stm32h757ai-cm4" ]
-stm32h757bi_cm7 = [ "stm32-metapac/stm32h757bi_cm7" ]
+stm32h757bi-cm7 = [ "stm32-metapac/stm32h757bi-cm7" ]
-stm32h757bi_cm4 = [ "stm32-metapac/stm32h757bi_cm4" ]
+stm32h757bi-cm4 = [ "stm32-metapac/stm32h757bi-cm4" ]
-stm32h757ii_cm7 = [ "stm32-metapac/stm32h757ii_cm7" ]
+stm32h757ii-cm7 = [ "stm32-metapac/stm32h757ii-cm7" ]
-stm32h757ii_cm4 = [ "stm32-metapac/stm32h757ii_cm4" ]
+stm32h757ii-cm4 = [ "stm32-metapac/stm32h757ii-cm4" ]
-stm32h757xi_cm7 = [ "stm32-metapac/stm32h757xi_cm7" ]
+stm32h757xi-cm7 = [ "stm32-metapac/stm32h757xi-cm7" ]
-stm32h757xi_cm4 = [ "stm32-metapac/stm32h757xi_cm4" ]
+stm32h757xi-cm4 = [ "stm32-metapac/stm32h757xi-cm4" ]
-stm32h757zi_cm7 = [ "stm32-metapac/stm32h757zi_cm7" ]
+stm32h757zi-cm7 = [ "stm32-metapac/stm32h757zi-cm7" ]
-stm32h757zi_cm4 = [ "stm32-metapac/stm32h757zi_cm4" ]
+stm32h757zi-cm4 = [ "stm32-metapac/stm32h757zi-cm4" ]
 stm32h7a3ag = [ "stm32-metapac/stm32h7a3ag" ]
 stm32h7a3ai = [ "stm32-metapac/stm32h7a3ai" ]
 stm32h7a3ig = [ "stm32-metapac/stm32h7a3ig" ]
@@ -1066,10 +1066,10 @@ stm32wb55vc = [ "stm32-metapac/stm32wb55vc" ]
 stm32wb55ve = [ "stm32-metapac/stm32wb55ve" ]
 stm32wb55vg = [ "stm32-metapac/stm32wb55vg" ]
 stm32wb55vy = [ "stm32-metapac/stm32wb55vy" ]
-stm32wl55cc_cm4 = [ "stm32-metapac/stm32wl55cc_cm4" ]
+stm32wl55cc-cm4 = [ "stm32-metapac/stm32wl55cc-cm4" ]
-stm32wl55cc_cm0p = [ "stm32-metapac/stm32wl55cc_cm0p" ]
+stm32wl55cc-cm0p = [ "stm32-metapac/stm32wl55cc-cm0p" ]
-stm32wl55jc_cm4 = [ "stm32-metapac/stm32wl55jc_cm4" ]
+stm32wl55jc-cm4 = [ "stm32-metapac/stm32wl55jc-cm4" ]
-stm32wl55jc_cm0p = [ "stm32-metapac/stm32wl55jc_cm0p" ]
+stm32wl55jc-cm0p = [ "stm32-metapac/stm32wl55jc-cm0p" ]
-stm32wl55uc_cm4 = [ "stm32-metapac/stm32wl55uc_cm4" ]
+stm32wl55uc-cm4 = [ "stm32-metapac/stm32wl55uc-cm4" ]
-stm32wl55uc_cm0p = [ "stm32-metapac/stm32wl55uc_cm0p" ]
+stm32wl55uc-cm0p = [ "stm32-metapac/stm32wl55uc-cm0p" ]
 # END GENERATED FEATURES

examples/stm32wl55/Cargo.toml

@@ -8,7 +8,7 @@ resolver = "2"
 [dependencies]
 embassy = { version = "0.1.0", path = "../../embassy", features = ["defmt"] }
 embassy-traits = { version = "0.1.0", path = "../../embassy-traits", features = ["defmt"] }
-embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["defmt", "stm32wl55jc_cm4", "time-driver-tim2", "memory-x", "subghz", "unstable-pac"]  }
+embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["defmt", "stm32wl55jc-cm4", "time-driver-tim2", "memory-x", "subghz", "unstable-pac"]  }
 embassy-hal-common = {version = "0.1.0", path = "../../embassy-hal-common" }
 embassy-lora = { version = "0.1.0", path = "../../embassy-lora", features = ["stm32wl", "time"] }
 

stm32-gen-features/src/lib.rs

@@ -123,7 +123,7 @@ pub fn stm32_metapac_needed_data(names_and_cores: &[(String, Vec<String>)]) -> S
     for (chip_name, cores) in names_and_cores {
         if cores.len() > 1 {
             for core_name in cores {
-                result += &format!("{}_{} = []\n", chip_name, core_name);
+                result += &format!("{}-{} = []\n", chip_name, core_name);
             }
         } else {
             result += &format!("{} = []\n", chip_name);

stm32-metapac-gen/src/assets/build.rs

@@ -1,30 +1,30 @@
 use std::env;
+use std::path::PathBuf;
 
 fn main() {
-    let chip_name = env::vars_os()
+    let crate_dir = PathBuf::from(env::var_os("CARGO_MANIFEST_DIR").unwrap());
+
+    let chip_core_name = env::vars_os()
         .map(|(a, _)| a.to_string_lossy().to_string())
         .find(|x| x.starts_with("CARGO_FEATURE_STM32"))
         .expect("No stm32xx Cargo feature enabled")
         .strip_prefix("CARGO_FEATURE_")
         .unwrap()
-        .to_ascii_lowercase();
+        .to_ascii_lowercase()
+        .replace('_', "-");
 
-    let mut s = chip_name.split('_');
+    println!(
-    let mut chip_name: String = s.next().unwrap().to_string();
+        "cargo:rustc-link-search={}/src/chips/{}",
-    if let Some(c) = s.next() {
+        crate_dir.display(),
-        if !c.starts_with("CM") {
+        chip_core_name,
-            chip_name.push('-');
+    );
-        } else {
-            chip_name.push('_');
-        }
-        chip_name.push_str(c);
-    }
 
     #[cfg(feature = "memory-x")]
-    println!("cargo:rustc-link-search=src/chips/{}/memory_x/", _chip_name);
+    println!(
-
+        "cargo:rustc-link-search={}/src/chips/{}/memory_x/",
-    #[cfg(feature = "rt")]
+        crate_dir.display(),
-    println!("cargo:rustc-link-search=src/chips/{}", _chip_name);
+        chip_core_name,
+    );
 
     println!("cargo:rerun-if-changed=build.rs");
 }

stm32-metapac-gen/src/lib.rs

@@ -2,7 +2,6 @@ use chiptool::generate::CommonModule;
 use chiptool::ir::IR;
 use regex::Regex;
 use std::collections::{BTreeMap, HashMap, HashSet};
-use std::env;
 use std::fmt::Write as _;
 use std::fs;
 use std::fs::File;
@@ -98,69 +97,14 @@ pub struct Options {
     pub data_dir: PathBuf,
 }
 
-pub fn gen(options: Options) {
+pub fn gen_chip(
-    let generate_opts = generate::Options {
+    options: &Options,
-        common_module: CommonModule::Builtin,
+    chip_core_name: &str,
-    };
+    chip: &Chip,
-
+    core: &Core,
-    let out_dir = options.out_dir;
+    core_index: usize,
-    let data_dir = options.data_dir;
+    all_peripheral_versions: &mut HashSet<(String, String)>,
-
+) {
-    fs::create_dir_all(out_dir.join("src/peripherals")).unwrap();
-    fs::create_dir_all(out_dir.join("src/chips")).unwrap();
-
-    println!("cwd: {:?}", env::current_dir());
-
-    let mut all_peripheral_versions: HashSet<(String, String)> = HashSet::new();
-    let mut chip_cores: BTreeMap<String, Option<String>> = BTreeMap::new();
-
-    for chip_name in &options.chips {
-        let mut s = chip_name.split('_');
-        let mut chip_name: String = s.next().unwrap().to_string();
-        let core_name: Option<&str> = if let Some(c) = s.next() {
-            if !c.starts_with("CM") {
-                println!("Core not detected, adding as variant");
-                chip_name.push('-');
-                chip_name.push_str(c);
-                None
-            } else {
-                println!("Detected core {}", c);
-                Some(c)
-            }
-        } else {
-            None
-        };
-
-        chip_cores.insert(
-            chip_name.to_string(),
-            core_name.map(|s| s.to_ascii_lowercase().to_string()),
-        );
-
-        let chip_path = data_dir.join("chips").join(&format!("{}.yaml", chip_name));
-        println!("chip_path: {:?}", chip_path);
-        let chip = fs::read(chip_path).unwrap();
-        let chip: Chip = serde_yaml::from_slice(&chip).unwrap();
-
-        println!("looking for core {:?}", core_name);
-        let core: Option<(&Core, usize)> = if let Some(core_name) = core_name {
-            let core_name = core_name.to_ascii_lowercase();
-            let mut c = None;
-            let mut idx = 0;
-            for (i, core) in chip.cores.iter().enumerate() {
-                if core.name == core_name {
-                    c = Some(core);
-                    idx = i;
-                    break;
-                }
-            }
-            c.map(|c| (c, idx))
-        } else {
-            Some((&chip.cores[0], 0))
-        };
-
-        let (core, core_index) = core.unwrap();
-        let core_name = &core.name;
-
     let mut ir = ir::IR::new();
 
     let mut dev = ir::Device {
@@ -173,7 +117,8 @@ pub fn gen(options: Options) {
         if name == "DBGMCU" {
             p.block.as_ref().map(|block| {
                 let bi = BlockInfo::parse(block);
-                    let dbgmcu_reg_path = data_dir
+                let dbgmcu_reg_path = options
+                    .data_dir
                     .join("registers")
                     .join(&format!("{}_{}.yaml", bi.module, bi.version));
                 serde_yaml::from_reader(File::open(dbgmcu_reg_path).unwrap()).unwrap()
@@ -192,7 +137,8 @@ pub fn gen(options: Options) {
 
     let rcc_block = rcc.block.as_ref().expect("RCC peripheral has no block");
     let bi = BlockInfo::parse(&rcc_block);
-        let rcc_reg_path = data_dir
+    let rcc_reg_path = options
+        .data_dir
         .join("registers")
         .join(&format!("{}_{}.yaml", bi.module, bi.version));
     let rcc: IR = serde_yaml::from_reader(File::open(rcc_reg_path).unwrap()).unwrap();
@@ -519,19 +465,15 @@ pub fn gen(options: Options) {
     transform::sort::Sort {}.run(&mut ir).unwrap();
     transform::Sanitize {}.run(&mut ir).unwrap();
 
-        let chip_dir = if chip.cores.len() > 1 {
+    let chip_dir = options
-            out_dir.join("src/chips").join(format!(
+        .out_dir
-                "{}_{}",
-                chip_name.to_ascii_lowercase(),
-                core_name.to_ascii_lowercase()
-            ))
-        } else {
-            out_dir
         .join("src/chips")
-                .join(chip_name.to_ascii_lowercase())
+        .join(chip_core_name.to_ascii_lowercase());
-        };
     fs::create_dir_all(&chip_dir).unwrap();
 
+    let generate_opts = generate::Options {
+        common_module: CommonModule::Builtin,
+    };
     let items = generate::render(&ir, &generate_opts).unwrap();
     let mut file = File::create(chip_dir.join("pac.rs")).unwrap();
     let data = items.to_string().replace("] ", "]\n");
@@ -562,10 +504,50 @@ pub fn gen(options: Options) {
     gen_memory_x(&chip_dir, &chip);
 }
 
+fn load_chip(options: &Options, name: &str) -> Chip {
+    let chip_path = options
+        .data_dir
+        .join("chips")
+        .join(&format!("{}.yaml", name));
+    let chip = fs::read(chip_path).expect(&format!("Could not load chip {}", name));
+    serde_yaml::from_slice(&chip).unwrap()
+}
+
+pub fn gen(options: Options) {
+    let generate_opts = generate::Options {
+        common_module: CommonModule::Builtin,
+    };
+
+    fs::create_dir_all(options.out_dir.join("src/peripherals")).unwrap();
+    fs::create_dir_all(options.out_dir.join("src/chips")).unwrap();
+
+    let mut all_peripheral_versions: HashSet<(String, String)> = HashSet::new();
+    let mut chip_core_names: Vec<String> = Vec::new();
+
+    for chip_name in &options.chips {
+        let chip = load_chip(&options, chip_name);
+        for (core_index, core) in chip.cores.iter().enumerate() {
+            let chip_core_name = match chip.cores.len() {
+                1 => chip_name.clone(),
+                _ => format!("{}-{}", chip_name, core.name),
+            };
+
+            chip_core_names.push(chip_core_name.clone());
+            gen_chip(
+                &options,
+                &chip_core_name,
+                &chip,
+                core,
+                core_index,
+                &mut all_peripheral_versions,
+            )
+        }
+    }
+
     for (module, version) in all_peripheral_versions {
         println!("loading {} {}", module, version);
 
-        let regs_path = Path::new(&data_dir)
+        let regs_path = Path::new(&options.data_dir)
             .join("registers")
             .join(&format!("{}_{}.yaml", module, version));
 
@@ -587,7 +569,8 @@ pub fn gen(options: Options) {
 
         let items = generate::render(&ir, &generate_opts).unwrap();
         let mut file = File::create(
-            out_dir
+            options
+                .out_dir
                 .join("src/peripherals")
                 .join(format!("{}_{}.rs", module, version)),
         )
@@ -606,16 +589,8 @@ pub fn gen(options: Options) {
     let i = bytes_find(librs, PATHS_MARKER).unwrap();
     let mut paths = String::new();
 
-    for (chip, cores) in chip_cores.iter() {
+    for name in chip_core_names {
-        let x = chip.to_ascii_lowercase();
+        let x = name.to_ascii_lowercase();
-        if let Some(c) = cores {
-            write!(
-                &mut paths,
-                "#[cfg_attr(feature=\"{}_{}\", path = \"chips/{}_{}/pac.rs\")]",
-                x, c, x, c
-            )
-            .unwrap();
-        } else {
         write!(
             &mut paths,
             "#[cfg_attr(feature=\"{}\", path = \"chips/{}/pac.rs\")]",
@@ -623,12 +598,11 @@ pub fn gen(options: Options) {
         )
         .unwrap();
     }
-    }
     let mut contents: Vec<u8> = Vec::new();
     contents.extend(&librs[..i]);
     contents.extend(paths.as_bytes());
     contents.extend(&librs[i + PATHS_MARKER.len()..]);
-    fs::write(out_dir.join("src").join("lib_inner.rs"), &contents).unwrap();
+    fs::write(options.out_dir.join("src").join("lib_inner.rs"), &contents).unwrap();
 
     // Generate src/lib.rs
     const CUT_MARKER: &[u8] = b"// GEN CUT HERE";
@@ -637,11 +611,11 @@ pub fn gen(options: Options) {
     let mut contents: Vec<u8> = Vec::new();
     contents.extend(&librs[..i]);
     contents.extend(b"include!(\"lib_inner.rs\");\n");
-    fs::write(out_dir.join("src").join("lib.rs"), contents).unwrap();
+    fs::write(options.out_dir.join("src").join("lib.rs"), contents).unwrap();
 
     // Generate src/common.rs
     fs::write(
-        out_dir.join("src").join("common.rs"),
+        options.out_dir.join("src").join("common.rs"),
         generate::COMMON_MODULE,
     )
     .unwrap();
@@ -654,10 +628,14 @@ pub fn gen(options: Options) {
     let begin = bytes_find(&contents, BUILDDEP_BEGIN).unwrap();
     let end = bytes_find(&contents, BUILDDEP_END).unwrap() + BUILDDEP_END.len();
     contents.drain(begin..end);
-    fs::write(out_dir.join("Cargo.toml"), contents).unwrap();
+    fs::write(options.out_dir.join("Cargo.toml"), contents).unwrap();
 
     // Generate build.rs
-    fs::write(out_dir.join("build.rs"), include_bytes!("assets/build.rs")).unwrap();
+    fs::write(
+        options.out_dir.join("build.rs"),
+        include_bytes!("assets/build.rs"),
+    )
+    .unwrap();
 }
 
 fn bytes_find(haystack: &[u8], needle: &[u8]) -> Option<usize> {

stm32-metapac-gen/src/main.rs

@@ -17,7 +17,6 @@ fn main() {
                 .unwrap()
                 .filter_map(|res| res.unwrap().file_name().to_str().map(|s| s.to_string()))
                 .filter(|s| s.ends_with(".yaml"))
-                .filter(|s| !s.starts_with("STM32L1")) // cursed gpio stride
                 .filter(|s| !s.starts_with("STM32GBK")) // cursed weird STM32G4
                 .map(|s| s.strip_suffix(".yaml").unwrap().to_string())
                 .collect()

stm32-metapac/Cargo.toml

@@ -780,40 +780,40 @@ stm32h743xg = []
 stm32h743xi = []
 stm32h743zg = []
 stm32h743zi = []
-stm32h745bg_cm7 = []
+stm32h745bg-cm7 = []
-stm32h745bg_cm4 = []
+stm32h745bg-cm4 = []
-stm32h745bi_cm7 = []
+stm32h745bi-cm7 = []
-stm32h745bi_cm4 = []
+stm32h745bi-cm4 = []
-stm32h745ig_cm7 = []
+stm32h745ig-cm7 = []
-stm32h745ig_cm4 = []
+stm32h745ig-cm4 = []
-stm32h745ii_cm7 = []
+stm32h745ii-cm7 = []
-stm32h745ii_cm4 = []
+stm32h745ii-cm4 = []
-stm32h745xg_cm7 = []
+stm32h745xg-cm7 = []
-stm32h745xg_cm4 = []
+stm32h745xg-cm4 = []
-stm32h745xi_cm7 = []
+stm32h745xi-cm7 = []
-stm32h745xi_cm4 = []
+stm32h745xi-cm4 = []
-stm32h745zg_cm7 = []
+stm32h745zg-cm7 = []
-stm32h745zg_cm4 = []
+stm32h745zg-cm4 = []
-stm32h745zi_cm7 = []
+stm32h745zi-cm7 = []
-stm32h745zi_cm4 = []
+stm32h745zi-cm4 = []
-stm32h747ag_cm7 = []
+stm32h747ag-cm7 = []
-stm32h747ag_cm4 = []
+stm32h747ag-cm4 = []
-stm32h747ai_cm7 = []
+stm32h747ai-cm7 = []
-stm32h747ai_cm4 = []
+stm32h747ai-cm4 = []
-stm32h747bg_cm7 = []
+stm32h747bg-cm7 = []
-stm32h747bg_cm4 = []
+stm32h747bg-cm4 = []
-stm32h747bi_cm7 = []
+stm32h747bi-cm7 = []
-stm32h747bi_cm4 = []
+stm32h747bi-cm4 = []
-stm32h747ig_cm7 = []
+stm32h747ig-cm7 = []
-stm32h747ig_cm4 = []
+stm32h747ig-cm4 = []
-stm32h747ii_cm7 = []
+stm32h747ii-cm7 = []
-stm32h747ii_cm4 = []
+stm32h747ii-cm4 = []
-stm32h747xg_cm7 = []
+stm32h747xg-cm7 = []
-stm32h747xg_cm4 = []
+stm32h747xg-cm4 = []
-stm32h747xi_cm7 = []
+stm32h747xi-cm7 = []
-stm32h747xi_cm4 = []
+stm32h747xi-cm4 = []
-stm32h747zi_cm7 = []
+stm32h747zi-cm7 = []
-stm32h747zi_cm4 = []
+stm32h747zi-cm4 = []
 stm32h750ib = []
 stm32h750vb = []
 stm32h750xb = []
@@ -824,24 +824,24 @@ stm32h753ii = []
 stm32h753vi = []
 stm32h753xi = []
 stm32h753zi = []
-stm32h755bi_cm7 = []
+stm32h755bi-cm7 = []
-stm32h755bi_cm4 = []
+stm32h755bi-cm4 = []
-stm32h755ii_cm7 = []
+stm32h755ii-cm7 = []
-stm32h755ii_cm4 = []
+stm32h755ii-cm4 = []
-stm32h755xi_cm7 = []
+stm32h755xi-cm7 = []
-stm32h755xi_cm4 = []
+stm32h755xi-cm4 = []
-stm32h755zi_cm7 = []
+stm32h755zi-cm7 = []
-stm32h755zi_cm4 = []
+stm32h755zi-cm4 = []
-stm32h757ai_cm7 = []
+stm32h757ai-cm7 = []
-stm32h757ai_cm4 = []
+stm32h757ai-cm4 = []
-stm32h757bi_cm7 = []
+stm32h757bi-cm7 = []
-stm32h757bi_cm4 = []
+stm32h757bi-cm4 = []
-stm32h757ii_cm7 = []
+stm32h757ii-cm7 = []
-stm32h757ii_cm4 = []
+stm32h757ii-cm4 = []
-stm32h757xi_cm7 = []
+stm32h757xi-cm7 = []
-stm32h757xi_cm4 = []
+stm32h757xi-cm4 = []
-stm32h757zi_cm7 = []
+stm32h757zi-cm7 = []
-stm32h757zi_cm4 = []
+stm32h757zi-cm4 = []
 stm32h7a3ag = []
 stm32h7a3ai = []
 stm32h7a3ig = []
@@ -1255,16 +1255,16 @@ stm32wb55ve = []
 stm32wb55vg = []
 stm32wb55vy = []
 stm32wb5mmg = []
-stm32wl54cc_cm4 = []
+stm32wl54cc-cm4 = []
-stm32wl54cc_cm0p = []
+stm32wl54cc-cm0p = []
-stm32wl54jc_cm4 = []
+stm32wl54jc-cm4 = []
-stm32wl54jc_cm0p = []
+stm32wl54jc-cm0p = []
-stm32wl55cc_cm4 = []
+stm32wl55cc-cm4 = []
-stm32wl55cc_cm0p = []
+stm32wl55cc-cm0p = []
-stm32wl55jc_cm4 = []
+stm32wl55jc-cm4 = []
-stm32wl55jc_cm0p = []
+stm32wl55jc-cm0p = []
-stm32wl55uc_cm4 = []
+stm32wl55uc-cm4 = []
-stm32wl55uc_cm0p = []
+stm32wl55uc-cm0p = []
 stm32wle4c8 = []
 stm32wle4cb = []
 stm32wle4cc = []

stm32-metapac/build.rs

@@ -2,48 +2,52 @@ use std::env;
 use std::path::PathBuf;
 use stm32_metapac_gen::*;
 
+fn parse_chip_core(chip_and_core: &str) -> (String, Option<String>) {
+    let mut s = chip_and_core.split('-');
+    let chip_name: String = s.next().unwrap().to_string();
+    if let Some(c) = s.next() {
+        if c.starts_with("CM") {
+            return (chip_name, Some(c.to_ascii_lowercase()));
+        }
+    }
+
+    (chip_and_core.to_string(), None)
+}
+
 fn main() {
     let out_dir = PathBuf::from(env::var_os("OUT_DIR").unwrap());
     let data_dir = PathBuf::from("../stm32-data/data");
 
     println!("cwd: {:?}", env::current_dir());
 
-    let chip_name = env::vars_os()
+    let chip_core_name = env::vars_os()
         .map(|(a, _)| a.to_string_lossy().to_string())
         .find(|x| x.starts_with("CARGO_FEATURE_STM32"))
         .expect("No stm32xx Cargo feature enabled")
         .strip_prefix("CARGO_FEATURE_")
         .unwrap()
-        .to_ascii_uppercase();
+        .to_ascii_uppercase()
+        .replace('_', "-");
+
+    let (chip_name, _) = parse_chip_core(&chip_core_name);
 
     gen(Options {
         out_dir: out_dir.clone(),
         data_dir: data_dir.clone(),
-        chips: vec![chip_name.clone()],
+        chips: vec![chip_name],
     });
 
-    let mut s = chip_name.split('_');
-    let mut chip_name: String = s.next().unwrap().to_string();
-    if let Some(c) = s.next() {
-        if !c.starts_with("CM") {
-            chip_name.push('-');
-        } else {
-            chip_name.push('_');
-        }
-        chip_name.push_str(c);
-    }
-
     println!(
         "cargo:rustc-link-search={}/src/chips/{}",
         out_dir.display(),
-        chip_name.to_ascii_lowercase()
+        chip_core_name.to_ascii_lowercase()
     );
 
     #[cfg(feature = "memory-x")]
     println!(
         "cargo:rustc-link-search={}/src/chips/{}/memory_x/",
         out_dir.display(),
-        chip_name.to_ascii_lowercase()
+        chip_core_name.to_ascii_lowercase()
     );
 
     println!("cargo:rerun-if-changed=build.rs");