Work done

cyw43-pio/Cargo.toml

@@ -13,8 +13,6 @@ documentation = "https://docs.embassy.dev/cyw43-pio"
 # If disabled, SPI runs at 31.25MHz
 # If enabled, SPI runs at 62.5MHz, which is 25% higher than 50Mhz which is the maximum according to the CYW43439 datasheet.
 overclock = []
-# If enabled the PIO runs at a speed that works with the rm2 module
-rm2 = []
 
 [dependencies]
 cyw43 = { version = "0.2.0", path = "../cyw43" }

cyw43-pio/src/lib.rs

@@ -10,6 +10,7 @@ use embassy_rp::dma::Channel;
 use embassy_rp::gpio::{Drive, Level, Output, Pull, SlewRate};
 use embassy_rp::pio::{instr, Common, Config, Direction, Instance, Irq, PioPin, ShiftDirection, StateMachine};
 use embassy_rp::{Peripheral, PeripheralRef};
+use fixed::types::extra::U8;
 use fixed::FixedU32;
 use pio_proc::pio_asm;
 
@@ -22,6 +23,26 @@ pub struct PioSpi<'d, PIO: Instance, const SM: usize, DMA> {
     wrap_target: u8,
 }
 
+/// The default clock divider that works for Pico 1 and 2 W. As well as the RM2 on rp2040 devices.
+/// same speed as pico-sdk, 62.5Mhz
+/// This is actually the fastest we can go without overclocking.
+/// According to data sheet, the theoretical maximum is 100Mhz Pio => 50Mhz SPI Freq.
+/// However, the PIO uses a fractional divider, which works by introducing jitter when
+/// the divider is not an integer. It does some clocks at 125mhz and others at 62.5mhz
+/// so that it averages out to the desired frequency of 100mhz. The 125mhz clock cycles
+/// violate the maximum from the data sheet.
+pub const DEFAULT_CLOCK_DIVIDER: FixedU32<U8> = FixedU32::from_bits(0x0200);
+
+/// The overclock clock divider for the Pico 1 W. Does not work on any known RM2 devices.
+/// 125mhz Pio => 62.5Mhz SPI Freq. 25% higher than theoretical maximum according to
+/// data sheet, but seems to work fine.
+pub const OVERCLOCK_CLOCK_DIVIDER: FixedU32<U8> = FixedU32::from_bits(0x0100);
+
+/// The clock divider for the RM2 module. Found to be needed for the Pimoroni Pico Plus 2 W,
+/// Pico Plus 2 Non w with the RM2 breakout module, and the Pico 2 with the RM2 breakout module.
+/// Does not work with the feature "overclock".
+pub const RM2_CLOCK_DIVIDER: FixedU32<U8> = FixedU32::from_bits(0x0300);
+
 impl<'d, PIO, const SM: usize, DMA> PioSpi<'d, PIO, SM, DMA>
 where
     DMA: Channel,
@@ -31,6 +52,7 @@ where
     pub fn new<DIO, CLK>(
         common: &mut Common<'d, PIO>,
         mut sm: StateMachine<'d, PIO, SM>,
+        clock_divider: FixedU32<U8>,
         irq: Irq<'d, PIO, 0>,
         cs: Output<'d>,
         dio: DIO,
@@ -112,31 +134,7 @@ where
         cfg.shift_in.direction = ShiftDirection::Left;
         cfg.shift_in.auto_fill = true;
         //cfg.shift_in.threshold = 32;
-
+        cfg.clock_divider = clock_divider;
-        #[cfg(feature = "overclock")]
-        {
-            // 125mhz Pio => 62.5Mhz SPI Freq. 25% higher than theoretical maximum according to
-            // data sheet, but seems to work fine.
-            cfg.clock_divider = FixedU32::from_bits(0x0100);
-        }
-
-        #[cfg(not(any(feature = "overclock", feature = "rm2")))]
-        {
-            // same speed as pico-sdk, 62.5Mhz
-            // This is actually the fastest we can go without overclocking.
-            // According to data sheet, the theoretical maximum is 100Mhz Pio => 50Mhz SPI Freq.
-            // However, the PIO uses a fractional divider, which works by introducing jitter when
-            // the divider is not an integer. It does some clocks at 125mhz and others at 62.5mhz
-            // so that it averages out to the desired frequency of 100mhz. The 125mhz clock cycles
-            // violate the maximum from the data sheet.
-            cfg.clock_divider = FixedU32::from_bits(0x0200);
-        }
-
-        #[cfg(feature = "rm2")]
-        {
-            // This is found to work better with the RM2 module which is found on the Pimoroni Pico Plus 2 W
-            cfg.clock_divider = FixedU32::from_bits(0x0300);
-        }
 
         sm.set_config(&cfg);