Merge #1197
1197: fix(stm32): Align FMC with new versions from stm32-data r=lulf a=rmja Co-authored-by: Rasmus Melchior Jacobsen <rmja@laesoe.org>
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				| @ -27,9 +27,13 @@ where | |||||||
|     } |     } | ||||||
| 
 | 
 | ||||||
|     fn memory_controller_enable(&mut self) { |     fn memory_controller_enable(&mut self) { | ||||||
|         // The FMCEN bit of the FMC_BCR2..4 registers is don’t
 |         // fmc v1 and v2 does not have the fmcen bit
 | ||||||
|         // care. It is only enabled through the FMC_BCR1 register.
 |         // fsmc v1, v2 and v3 does not have the fmcen bit
 | ||||||
|         unsafe { T::regs().bcr1().modify(|r| r.set_fmcen(true)) }; |         // This is a "not" because it is expected that all future versions have this bit
 | ||||||
|  |         #[cfg(not(any(fmc_v1x3, fmc_v2x1, fsmc_v1x0, fsmc_v1x3, fsmc_v2x3, fsmc_v3x1)))] | ||||||
|  |         unsafe { | ||||||
|  |             T::regs().bcr1().modify(|r| r.set_fmcen(true)) | ||||||
|  |         }; | ||||||
|     } |     } | ||||||
| 
 | 
 | ||||||
|     fn source_clock_hz(&self) -> u32 { |     fn source_clock_hz(&self) -> u32 { | ||||||
|  | |||||||
| @ -1 +1 @@ | |||||||
| Subproject commit 96decdd6114d78813c1f748fb878a45e1b03bf73 | Subproject commit cc93f9d10395077770bebefb6b9488e06b0e5811 | ||||||
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