From ee25f14b20fc2aabf428fbc7b2bd684ece66a2a1 Mon Sep 17 00:00:00 2001
From: Badr Bouslikhin <bouslikhin.badr@gmail.com>
Date: Fri, 6 Sep 2024 18:35:23 +0200
Subject: [PATCH 1/2] fix(stm32): reorder dma and idle futures

---
 embassy-stm32/src/usart/ringbuffered.rs | 34 ++++++++++++-------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/embassy-stm32/src/usart/ringbuffered.rs b/embassy-stm32/src/usart/ringbuffered.rs
index 8cf75933a..b0652046c 100644
--- a/embassy-stm32/src/usart/ringbuffered.rs
+++ b/embassy-stm32/src/usart/ringbuffered.rs
@@ -184,20 +184,6 @@ impl<'d> RingBufferedUartRx<'d> {
     async fn wait_for_data_or_idle(&mut self) -> Result<(), Error> {
         compiler_fence(Ordering::SeqCst);
 
-        let mut dma_init = false;
-        // Future which completes when there is dma is half full or full
-        let dma = poll_fn(|cx| {
-            self.ring_buf.set_waker(cx.waker());
-
-            let status = match dma_init {
-                false => Poll::Pending,
-                true => Poll::Ready(()),
-            };
-
-            dma_init = true;
-            status
-        });
-
         // Future which completes when idle line is detected
         let s = self.state;
         let uart = poll_fn(|cx| {
@@ -219,9 +205,23 @@ impl<'d> RingBufferedUartRx<'d> {
             }
         });
 
-        match select(dma, uart).await {
-            Either::Left(((), _)) => Ok(()),
-            Either::Right((result, _)) => result,
+        let mut dma_init = false;
+        // Future which completes when there is dma is half full or full
+        let dma = poll_fn(|cx| {
+            self.ring_buf.set_waker(cx.waker());
+
+            let status = match dma_init {
+                false => Poll::Pending,
+                true => Poll::Ready(()),
+            };
+
+            dma_init = true;
+            status
+        });
+
+        match select(uart, dma).await {
+            Either::Left((result, _)) => result,
+            Either::Right(((), _)) => Ok(()),
         }
     }
 }

From 0e477a4df506981e770e41edec31e2bc0cd6b6c6 Mon Sep 17 00:00:00 2001
From: Badr Bouslikhin <bouslikhin.badr@gmail.com>
Date: Fri, 6 Sep 2024 18:36:11 +0200
Subject: [PATCH 2/2] fix(stm32): enable dma half transfer interrupt for
 buffereduart

---
 embassy-stm32/src/dma/dma_bdma.rs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/embassy-stm32/src/dma/dma_bdma.rs b/embassy-stm32/src/dma/dma_bdma.rs
index 8e2964f94..df041c4e9 100644
--- a/embassy-stm32/src/dma/dma_bdma.rs
+++ b/embassy-stm32/src/dma/dma_bdma.rs
@@ -777,6 +777,7 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W> {
         let dir = Dir::PeripheralToMemory;
         let data_size = W::size();
 
+        options.half_transfer_ir = true;
         options.complete_transfer_ir = true;
         options.circular = true;