From ce04cf83407f0c70d7d1eec4ed1de2dfbef06dd6 Mon Sep 17 00:00:00 2001 From: vinsynth <1.5vhunt@gmail.com> Date: Sun, 2 Feb 2025 18:12:34 -0500 Subject: [PATCH] set PLLI2S M and SRC for f4 chips which support it --- embassy-stm32/src/rcc/f247.rs | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/embassy-stm32/src/rcc/f247.rs b/embassy-stm32/src/rcc/f247.rs index 3e7aff02d..b855d3c09 100644 --- a/embassy-stm32/src/rcc/f247.rs +++ b/embassy-stm32/src/rcc/f247.rs @@ -414,6 +414,11 @@ fn init_pll(instance: PllInstance, config: Option, input: &PllInput) -> Pll }), #[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))] PllInstance::Plli2s => RCC.plli2scfgr().write(|w| { + #[cfg(any(stm32f411, stm32f412, stm32f413, stm32f446))] + w.set_pllm(pll.prediv); + #[cfg(any(stm32f412, stm32f413))] + w.set_pllsrc(input.source); + write_fields!(w); }), #[cfg(stm32f2)]