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Merge pull request #2060 from xoviat/rcc

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stm32: expand rcc mux to g4 and h7
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xoviat 2023-10-15 04:37:36 +00:00 committed by GitHub
commit cd92bc3145
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6 changed files with 72 additions and 74 deletions
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4
embassy-stm32/Cargo.toml
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@ -58,7 +58,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0" sdio-host = "0.5.0"
embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true } embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
critical-section = "1.1" critical-section = "1.1"
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-e6e51db6cdd7d533e52ca7a3237f7816a0486cd4" } stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7dafe9d8bbc739be48199185f0caa1582b1da3f7" }
vcell = "0.1.3" vcell = "0.1.3"
bxcan = "0.7.0" bxcan = "0.7.0"
nb = "1.0.0" nb = "1.0.0"
@ -76,7 +76,7 @@ critical-section = { version = "1.1", features = ["std"] }
[build-dependencies] [build-dependencies]
proc-macro2 = "1.0.36" proc-macro2 = "1.0.36"
quote = "1.0.15" quote = "1.0.15"
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-e6e51db6cdd7d533e52ca7a3237f7816a0486cd4", default-features = false, features = ["metadata"]} stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-7dafe9d8bbc739be48199185f0caa1582b1da3f7", default-features = false, features = ["metadata"]}
[features] [features]

43
embassy-stm32/build.rs
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@ -388,20 +388,21 @@ fn main() {
}); });
} }
// ========
// Extract the rcc registers
let rcc_registers = METADATA
.peripherals
.iter()
.filter_map(|p| p.registers.as_ref())
.find(|r| r.kind == "rcc")
.unwrap();
// ======== // ========
// Generate rcc fieldset and enum maps // Generate rcc fieldset and enum maps
let rcc_enum_map: HashMap<&str, HashMap<&str, &Enum>> = { let rcc_enum_map: HashMap<&str, HashMap<&str, &Enum>> = {
let rcc_registers = METADATA let rcc_blocks = rcc_registers.ir.blocks.iter().find(|b| b.name == "Rcc").unwrap().items;
.peripherals let rcc_fieldsets: HashMap<&str, &FieldSet> = rcc_registers.ir.fieldsets.iter().map(|f| (f.name, f)).collect();
.iter() let rcc_enums: HashMap<&str, &Enum> = rcc_registers.ir.enums.iter().map(|e| (e.name, e)).collect();
.filter_map(|p| p.registers.as_ref())
.find(|r| r.kind == "rcc")
.unwrap()
.ir;
let rcc_blocks = rcc_registers.blocks.iter().find(|b| b.name == "Rcc").unwrap().items;
let rcc_fieldsets: HashMap<&str, &FieldSet> = rcc_registers.fieldsets.iter().map(|f| (f.name, f)).collect();
let rcc_enums: HashMap<&str, &Enum> = rcc_registers.enums.iter().map(|e| (e.name, e)).collect();
rcc_blocks rcc_blocks
.iter() .iter()
@ -494,8 +495,10 @@ fn main() {
}; };
let mux_for = |mux: Option<&'static PeripheralRccRegister>| { let mux_for = |mux: Option<&'static PeripheralRccRegister>| {
// temporary hack to restrict the scope of the implementation to h5 let checked_rccs = HashSet::from(["h5", "h50", "h7", "h7ab", "h7rm0433", "g4"]);
if !&chip_name.starts_with("stm32h5") {
// restrict mux implementation to supported versions
if !checked_rccs.contains(rcc_registers.version) {
return None; return None;
} }
@ -518,11 +521,9 @@ fn main() {
.filter(|v| v.name != "DISABLE") .filter(|v| v.name != "DISABLE")
.map(|v| { .map(|v| {
let variant_name = format_ident!("{}", v.name); let variant_name = format_ident!("{}", v.name);
// temporary hack to restrict the scope of the implementation until clock names can be stabilized
let clock_name = format_ident!("{}", v.name.to_ascii_lowercase()); let clock_name = format_ident!("{}", v.name.to_ascii_lowercase());
if v.name.starts_with("AHB") || v.name.starts_with("APB") { if v.name.starts_with("AHB") || v.name.starts_with("APB") || v.name == "SYS" {
quote! { quote! {
#enum_name::#variant_name => unsafe { crate::rcc::get_freqs().#clock_name }, #enum_name::#variant_name => unsafe { crate::rcc::get_freqs().#clock_name },
} }
@ -1013,15 +1014,7 @@ fn main() {
// ======== // ========
// Generate Div/Mul impls for RCC prescalers/dividers/multipliers. // Generate Div/Mul impls for RCC prescalers/dividers/multipliers.
let rcc_registers = METADATA for e in rcc_registers.ir.enums {
.peripherals
.iter()
.filter_map(|p| p.registers.as_ref())
.find(|r| r.kind == "rcc")
.unwrap()
.ir;
for e in rcc_registers.enums {
fn is_rcc_name(e: &str) -> bool { fn is_rcc_name(e: &str) -> bool {
match e { match e {
"Pllp" | "Pllq" | "Pllr" | "Pllm" | "Plln" => true, "Pllp" | "Pllq" | "Pllr" | "Pllm" | "Plln" => true,

17
embassy-stm32/src/rcc/g4.rs
View File

@ -119,8 +119,8 @@ impl Default for Config {
low_power_run: false, low_power_run: false,
pll: None, pll: None,
clock_48mhz_src: None, clock_48mhz_src: None,
adc12_clock_source: Adcsel::NOCLK, adc12_clock_source: Adcsel::DISABLE,
adc345_clock_source: Adcsel::NOCLK, adc345_clock_source: Adcsel::DISABLE,
ls: Default::default(), ls: Default::default(),
} }
} }
@ -326,16 +326,16 @@ pub(crate) unsafe fn init(config: Config) {
RCC.ccipr().modify(|w| w.set_adc345sel(config.adc345_clock_source)); RCC.ccipr().modify(|w| w.set_adc345sel(config.adc345_clock_source));
let adc12_ck = match config.adc12_clock_source { let adc12_ck = match config.adc12_clock_source {
AdcClockSource::NOCLK => None, AdcClockSource::DISABLE => None,
AdcClockSource::PLLP => pll_freq.as_ref().unwrap().pll_p, AdcClockSource::PLL1_P => pll_freq.as_ref().unwrap().pll_p,
AdcClockSource::SYSCLK => Some(sys_clk), AdcClockSource::SYS => Some(sys_clk),
_ => unreachable!(), _ => unreachable!(),
}; };
let adc345_ck = match config.adc345_clock_source { let adc345_ck = match config.adc345_clock_source {
AdcClockSource::NOCLK => None, AdcClockSource::DISABLE => None,
AdcClockSource::PLLP => pll_freq.as_ref().unwrap().pll_p, AdcClockSource::PLL1_P => pll_freq.as_ref().unwrap().pll_p,
AdcClockSource::SYSCLK => Some(sys_clk), AdcClockSource::SYS => Some(sys_clk),
_ => unreachable!(), _ => unreachable!(),
}; };
@ -356,6 +356,7 @@ pub(crate) unsafe fn init(config: Config) {
apb2_tim: apb2_tim_freq, apb2_tim: apb2_tim_freq,
adc: adc12_ck, adc: adc12_ck,
adc34: adc345_ck, adc34: adc345_ck,
pll1_p: None,
rtc, rtc,
}); });
} }

33
embassy-stm32/src/rcc/h.rs
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@ -446,7 +446,7 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(stm32h5)] #[cfg(stm32h5)]
let adc = match config.adc_clock_source { let adc = match config.adc_clock_source {
AdcClockSource::HCLK => Some(hclk), AdcClockSource::HCLK => Some(hclk),
AdcClockSource::SYSCLK => Some(sys), AdcClockSource::SYS => Some(sys),
AdcClockSource::PLL2_R => pll2.r, AdcClockSource::PLL2_R => pll2.r,
AdcClockSource::HSE => hse, AdcClockSource::HSE => hse,
AdcClockSource::HSI => hsi, AdcClockSource::HSI => hsi,
@ -540,36 +540,34 @@ pub(crate) unsafe fn init(config: Config) {
adc, adc,
rtc, rtc,
#[cfg(stm32h5)] #[cfg(any(stm32h5, stm32h7))]
hsi: None, hsi: None,
#[cfg(stm32h5)] #[cfg(stm32h5)]
hsi48: None, hsi48: None,
#[cfg(stm32h5)] #[cfg(stm32h5)]
lsi: None, lsi: None,
#[cfg(stm32h5)] #[cfg(any(stm32h5, stm32h7))]
csi: None, csi: None,
#[cfg(stm32h5)] #[cfg(any(stm32h5, stm32h7))]
lse: None, lse: None,
#[cfg(stm32h5)] #[cfg(any(stm32h5, stm32h7))]
hse: None, hse: None,
#[cfg(stm32h5)] #[cfg(any(stm32h5, stm32h7))]
pll1_q: pll1.q, pll1_q: pll1.q,
#[cfg(stm32h5)] #[cfg(any(stm32h5, stm32h7))]
pll2_q: pll2.q,
#[cfg(stm32h5)]
pll2_p: pll2.p, pll2_p: pll2.p,
#[cfg(stm32h5)] #[cfg(any(stm32h5, stm32h7))]
pll2_q: pll2.q,
#[cfg(any(stm32h5, stm32h7))]
pll2_r: pll2.r, pll2_r: pll2.r,
#[cfg(rcc_h5)] #[cfg(any(rcc_h5, stm32h7))]
pll3_p: pll3.p, pll3_p: pll3.p,
#[cfg(rcc_h5)] #[cfg(any(rcc_h5, stm32h7))]
pll3_q: pll3.q, pll3_q: pll3.q,
#[cfg(rcc_h5)] #[cfg(any(rcc_h5, stm32h7))]
pll3_r: pll3.r, pll3_r: pll3.r,
#[cfg(stm32h5)]
pll3_1: None,
#[cfg(rcc_h50)] #[cfg(rcc_h50)]
pll3_p: None, pll3_p: None,
@ -580,8 +578,11 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(stm32h5)] #[cfg(stm32h5)]
audioclk: None, audioclk: None,
#[cfg(stm32h5)] #[cfg(any(stm32h5, stm32h7))]
per: None, per: None,
#[cfg(stm32h7)]
rcc_pclk_d3: None,
}); });
} }

47
embassy-stm32/src/rcc/mod.rs
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@ -113,6 +113,23 @@ pub struct Clocks {
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))] #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
pub pllsai: Option<Hertz>, pub pllsai: Option<Hertz>,
#[cfg(stm32g4)]
pub pll1_p: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll1_q: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll2_q: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll2_p: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll2_r: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll3_p: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll3_q: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll3_r: Option<Hertz>,
#[cfg(any( #[cfg(any(
rcc_f1, rcc_f1,
rcc_f100, rcc_f100,
@ -135,41 +152,27 @@ pub struct Clocks {
pub rtc: Option<Hertz>, pub rtc: Option<Hertz>,
#[cfg(stm32h5)] #[cfg(any(stm32h5, stm32h7))]
pub hsi: Option<Hertz>, pub hsi: Option<Hertz>,
#[cfg(stm32h5)] #[cfg(stm32h5)]
pub hsi48: Option<Hertz>, pub hsi48: Option<Hertz>,
#[cfg(stm32h5)] #[cfg(stm32h5)]
pub lsi: Option<Hertz>, pub lsi: Option<Hertz>,
#[cfg(stm32h5)] #[cfg(any(stm32h5, stm32h7))]
pub csi: Option<Hertz>, pub csi: Option<Hertz>,
#[cfg(stm32h5)] #[cfg(any(stm32h5, stm32h7))]
pub lse: Option<Hertz>, pub lse: Option<Hertz>,
#[cfg(stm32h5)] #[cfg(any(stm32h5, stm32h7))]
pub hse: Option<Hertz>, pub hse: Option<Hertz>,
#[cfg(stm32h5)]
pub pll1_q: Option<Hertz>,
#[cfg(stm32h5)]
pub pll2_q: Option<Hertz>,
#[cfg(stm32h5)]
pub pll2_p: Option<Hertz>,
#[cfg(stm32h5)]
pub pll2_r: Option<Hertz>,
#[cfg(stm32h5)]
pub pll3_p: Option<Hertz>,
#[cfg(stm32h5)]
pub pll3_q: Option<Hertz>,
#[cfg(stm32h5)]
pub pll3_r: Option<Hertz>,
#[cfg(stm32h5)]
pub pll3_1: Option<Hertz>,
#[cfg(stm32h5)] #[cfg(stm32h5)]
pub audioclk: Option<Hertz>, pub audioclk: Option<Hertz>,
#[cfg(stm32h5)] #[cfg(any(stm32h5, stm32h7))]
pub per: Option<Hertz>, pub per: Option<Hertz>,
#[cfg(stm32h7)]
pub rcc_pclk_d3: Option<Hertz>,
} }
#[cfg(feature = "low-power")] #[cfg(feature = "low-power")]

2
examples/stm32g4/src/bin/adc.rs
View File

@ -24,7 +24,7 @@ async fn main(_spawner: Spawner) {
div_r: Some(PllR::DIV2), div_r: Some(PllR::DIV2),
}); });
config.rcc.adc12_clock_source = AdcClockSource::SYSCLK; config.rcc.adc12_clock_source = AdcClockSource::SYS;
config.rcc.mux = ClockSrc::PLL; config.rcc.mux = ClockSrc::PLL;
let mut p = embassy_stm32::init(config); let mut p = embassy_stm32::init(config);