SDMMC: Implement read and write
This commit is contained in:
Thales Fragoso
parent
490152d028
commit
c183c352c7
@ -1,5 +1,5 @@
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use core::marker::PhantomData;
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use core::task::{Context, Poll};
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use core::task::Poll;
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use embassy::interrupt::InterruptExt;
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use embassy::util::{AtomicWaker, OnDrop, Unborrow};
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@ -10,7 +10,7 @@ use sdio_host::{BusWidth, CardCapacity, CardStatus, CurrentState, SDStatus, CID,
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use crate::fmt::*;
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use crate::pac;
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use crate::pac::gpio::Gpio;
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use crate::pac::interrupt::{Interrupt, InterruptEnum};
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use crate::pac::interrupt::Interrupt;
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use crate::pac::sdmmc::Sdmmc as RegBlock;
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use crate::time::Hertz;
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@ -32,6 +32,9 @@ impl Default for Signalling {
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}
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}
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#[repr(align(4))]
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pub struct DataBlock([u8; 512]);
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/// Errors
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#[non_exhaustive]
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#[derive(Debug, Copy, Clone)]
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@ -201,16 +204,43 @@ impl<'d, T: Instance, P: Pins<T>> Sdmmc<'d, T, P> {
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.await
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}
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#[inline(always)]
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pub async fn read_block(
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&mut self,
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block_idx: u32,
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buffer: &mut DataBlock,
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) -> Result<(), Error> {
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let card_capacity = self.card()?.card_type;
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let inner = T::inner();
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let state = T::state();
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// NOTE(unsafe) DataBlock uses align 4
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let buf = unsafe { &mut *((&mut buffer.0) as *mut [u8; 512] as *mut [u32; 128]) };
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inner.read_block(block_idx, buf, card_capacity, state).await
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}
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pub async fn write_block(&mut self, block_idx: u32, buffer: &DataBlock) -> Result<(), Error> {
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let card = self.card.as_mut().ok_or(Error::NoCard)?;
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let inner = T::inner();
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let state = T::state();
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// NOTE(unsafe) DataBlock uses align 4
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let buf = unsafe { &*((&buffer.0) as *const [u8; 512] as *const [u32; 128]) };
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inner.write_block(block_idx, buf, card, state).await
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}
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/// Get a reference to the initialized card
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///
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/// # Errors
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///
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/// Returns Error::NoCard if [`init_card`](#method.init_card)
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/// has not previously succeeded
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#[inline(always)]
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pub fn card(&self) -> Result<&Card, Error> {
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self.card.as_ref().ok_or(Error::NoCard)
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}
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#[inline(always)]
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fn on_interrupt(_: *mut ()) {
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let regs = T::inner();
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let state = T::state();
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@ -260,7 +290,7 @@ impl SdmmcInner {
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/// Initializes card (if present) and sets the bus at the
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/// specified frequency.
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#[allow(clippy::too_many_arguments)]
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pub async fn init_card(
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async fn init_card(
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&self,
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freq: Hertz,
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bus_width: BusWidth,
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@ -397,8 +427,120 @@ impl SdmmcInner {
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Ok(())
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}
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async fn read_block(&mut self, block_idx: u32, buffer: &mut [u32; 128]) -> Result<(), Error> {
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self::todo!()
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async fn read_block(
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&self,
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block_idx: u32,
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buffer: &mut [u32; 128],
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capacity: CardCapacity,
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waker_reg: &AtomicWaker,
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) -> Result<(), Error> {
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// Always read 1 block of 512 bytes
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// SDSC cards are byte addressed hence the blockaddress is in multiples of 512 bytes
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let address = match capacity {
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CardCapacity::SDSC => block_idx * 512,
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_ => block_idx,
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};
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self.cmd(Cmd::set_block_length(512), false)?; // CMD16
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let regs = self.0;
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let on_drop = OnDrop::new(|| unsafe { self.on_drop() });
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let buf_addr = buffer as *mut [u32; 128] as u32;
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unsafe {
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self.prepare_datapath_transfer(buf_addr, 512, 9, Dir::CardToHost);
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self.data_interrupts(true);
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}
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self.cmd(Cmd::read_single_block(address), true)?;
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let res = poll_fn(|cx| {
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waker_reg.register(cx.waker());
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let status = unsafe { regs.star().read() };
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if status.dcrcfail() {
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return Poll::Ready(Err(Error::Crc));
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} else if status.dtimeout() {
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return Poll::Ready(Err(Error::Timeout));
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} else if status.dataend() {
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return Poll::Ready(Ok(()));
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}
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Poll::Pending
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})
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.await;
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self.clear_interrupt_flags();
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if res.is_ok() {
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on_drop.defuse();
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unsafe {
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regs.idmactrlr().modify(|w| w.set_idmaen(false));
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}
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}
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res
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}
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async fn write_block(
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&self,
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block_idx: u32,
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buffer: &[u32; 128],
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card: &mut Card,
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waker_reg: &AtomicWaker,
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) -> Result<(), Error> {
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// Always read 1 block of 512 bytes
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// SDSC cards are byte addressed hence the blockaddress is in multiples of 512 bytes
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let address = match card.card_type {
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CardCapacity::SDSC => block_idx * 512,
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_ => block_idx,
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};
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self.cmd(Cmd::set_block_length(512), false)?; // CMD16
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let regs = self.0;
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let on_drop = OnDrop::new(|| unsafe { self.on_drop() });
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let buf_addr = buffer as *const [u32; 128] as u32;
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unsafe {
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self.prepare_datapath_transfer(buf_addr, 512, 9, Dir::HostToCard);
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self.data_interrupts(true);
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}
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self.cmd(Cmd::write_single_block(address), true)?;
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let res = poll_fn(|cx| {
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waker_reg.register(cx.waker());
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let status = unsafe { regs.star().read() };
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if status.dcrcfail() {
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return Poll::Ready(Err(Error::Crc));
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} else if status.dtimeout() {
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return Poll::Ready(Err(Error::Timeout));
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} else if status.dataend() {
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return Poll::Ready(Ok(()));
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}
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Poll::Pending
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})
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.await;
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self.clear_interrupt_flags();
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match res {
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Ok(_) => {
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on_drop.defuse();
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unsafe {
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regs.idmactrlr().modify(|w| w.set_idmaen(false));
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}
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// TODO: Make this configurable
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let mut timeout: u32 = 0xFFFF_FFFF;
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// Try to read card status (ACMD13)
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while timeout > 0 {
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match self.read_sd_status(card, waker_reg).await {
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Ok(_) => return Ok(()),
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Err(Error::Timeout) => (), // Try again
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Err(e) => return Err(e),
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}
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timeout -= 1;
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}
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Err(Error::SoftwareTimeout)
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}
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Err(e) => Err(e),
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}
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}
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/// Get the current SDMMC bus clock
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@ -795,32 +937,13 @@ impl SdmmcInner {
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}
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}
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fn store_waker_and_unmask(
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&self,
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cx: &Context,
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interrupt_sdmmc1: bool,
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waker_reg: &AtomicWaker,
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) {
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use cortex_m::peripheral::NVIC;
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// NOTE(unsafe) We own the interrupt and can unmask it, it won't cause unsoundness
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unsafe {
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if interrupt_sdmmc1 {
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waker_reg.register(cx.waker());
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NVIC::unmask(InterruptEnum::SDMMC1);
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} else {
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waker_reg.register(cx.waker());
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NVIC::unmask(InterruptEnum::SDMMC2);
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}
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}
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}
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/// # Safety
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///
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/// Ensure that `regs` has exclusive access to the regblocks
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unsafe fn on_drop(&self) {
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let regs = self.0;
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if regs.star().read().dpsmact() {
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self.clear_interrupt_flags();
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// Send abort
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// CP state machine must be idle
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while regs.star().read().cpsmact() {}
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@ -890,9 +1013,9 @@ impl Cmd {
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}
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/// CMD12:
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const fn stop_transmission() -> Cmd {
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Cmd::new(12, 0, Response::Short)
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}
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//const fn stop_transmission() -> Cmd {
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// Cmd::new(12, 0, Response::Short)
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//}
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/// CMD13: Ask card to send status register
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/// ACMD13: SD Status
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@ -911,9 +1034,9 @@ impl Cmd {
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}
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/// CMD18: Multiple Block Read
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const fn read_multiple_blocks(addr: u32) -> Cmd {
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Cmd::new(18, addr, Response::Short)
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}
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//const fn read_multiple_blocks(addr: u32) -> Cmd {
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// Cmd::new(18, addr, Response::Short)
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//}
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/// CMD24: Block Write
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const fn write_single_block(addr: u32) -> Cmd {
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