Add further i2c error types
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				@ -114,7 +114,7 @@ pub unsafe fn init() {
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    reset::unreset_wait(peris);
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}
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pub(crate) fn clk_sys_freq() -> u32 {
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pub(crate) fn _clk_sys_freq() -> u32 {
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    125_000_000
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}
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@ -5,12 +5,25 @@ use pac::i2c;
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use crate::{pac, peripherals, Peripheral};
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/// I2C error abort reason
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum AbortReason {
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    /// A bus operation was not acknowledged, e.g. due to the addressed device
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    /// not being available on the bus or the device not being ready to process
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    /// requests at the moment
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    NoAcknowledge,
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    /// The arbitration was lost, e.g. electrical problems with the clock signal
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    ArbitrationLoss,
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    Other(u32),
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}
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/// I2C error
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Error {
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    /// I2C abort with error
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    Abort(u32),
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    Abort(AbortReason),
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    /// User passed in a read buffer that was 0 length
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    InvalidReadBufferLength,
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    /// User passed in a write buffer that was 0 length
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@ -29,9 +42,7 @@ pub struct Config {
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impl Default for Config {
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    fn default() -> Self {
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        Self {
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            frequency: 100_000,
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        }
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        Self { frequency: 100_000 }
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    }
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}
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@ -164,18 +175,30 @@ impl<'d, T: Instance, M: Mode> I2c<'d, T, M> {
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        Ok(())
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    }
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    fn read_and_clear_abort_reason(&mut self) -> Option<u32> {
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    fn read_and_clear_abort_reason(&mut self) -> Result<(), Error> {
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        let p = T::regs();
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        unsafe {
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            let abort_reason = p.ic_tx_abrt_source().read().0;
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            if abort_reason != 0 {
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            let abort_reason = p.ic_tx_abrt_source().read();
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            if abort_reason.0 != 0 {
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                // Note clearing the abort flag also clears the reason, and this
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                // instance of flag is clear-on-read! Note also the
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                // IC_CLR_TX_ABRT register always reads as 0.
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                p.ic_clr_tx_abrt().read();
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                Some(abort_reason)
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                let reason = if abort_reason.abrt_7b_addr_noack()
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                    | abort_reason.abrt_10addr1_noack()
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                    | abort_reason.abrt_10addr2_noack()
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                {
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                    AbortReason::NoAcknowledge
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                } else if abort_reason.arb_lost() {
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                    AbortReason::ArbitrationLoss
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                } else {
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                    AbortReason::Other(abort_reason.0)
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                };
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                Err(Error::Abort(reason))
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            } else {
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                None
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                Ok(())
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            }
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        }
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    }
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@ -204,9 +227,7 @@ impl<'d, T: Instance, M: Mode> I2c<'d, T, M> {
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                });
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                while p.ic_rxflr().read().rxflr() == 0 {
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                    if let Some(abort_reason) = self.read_and_clear_abort_reason() {
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                        return Err(Error::Abort(abort_reason));
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                    }
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                    self.read_and_clear_abort_reason()?;
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                }
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                *byte = p.ic_data_cmd().read().dat();
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@ -241,7 +262,7 @@ impl<'d, T: Instance, M: Mode> I2c<'d, T, M> {
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                let abort_reason = self.read_and_clear_abort_reason();
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                if abort_reason.is_some() || (send_stop && last) {
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                if abort_reason.is_err() || (send_stop && last) {
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                    // If the transaction was aborted or if it completed
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                    // successfully wait until the STOP condition has occured.
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@ -254,9 +275,7 @@ impl<'d, T: Instance, M: Mode> I2c<'d, T, M> {
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                // condition. Note also the hardware clears RX FIFO as well as
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                // TX on abort, ecause we set hwparam
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                // IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT to 0.
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                if let Some(abort_reason) = abort_reason {
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                    return Err(Error::Abort(abort_reason));
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                }
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                abort_reason?;
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            }
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        }
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        Ok(())
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@ -360,15 +379,15 @@ mod eh1 {
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    impl embedded_hal_1::i2c::Error for Error {
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        fn kind(&self) -> embedded_hal_1::i2c::ErrorKind {
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            match *self {
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                _ => embedded_hal_1::i2c::ErrorKind::Bus,
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                // Self::Arbitration => embedded_hal_1::i2c::ErrorKind::ArbitrationLoss,
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                // Self::Nack => {
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                //     embedded_hal_1::i2c::ErrorKind::NoAcknowledge(embedded_hal_1::i2c::NoAcknowledgeSource::Unknown)
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                // }
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                // Self::Timeout => embedded_hal_1::i2c::ErrorKind::Other,
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                // Self::Crc => embedded_hal_1::i2c::ErrorKind::Other,
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                // Self::Overrun => embedded_hal_1::i2c::ErrorKind::Overrun,
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                // Self::ZeroLengthTransfer => embedded_hal_1::i2c::ErrorKind::Other,
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                Self::Abort(AbortReason::ArbitrationLoss) => embedded_hal_1::i2c::ErrorKind::ArbitrationLoss,
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                Self::Abort(AbortReason::NoAcknowledge) => {
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                    embedded_hal_1::i2c::ErrorKind::NoAcknowledge(embedded_hal_1::i2c::NoAcknowledgeSource::Address)
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                }
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                Self::Abort(AbortReason::Other(_)) => embedded_hal_1::i2c::ErrorKind::Other,
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                Self::InvalidReadBufferLength => embedded_hal_1::i2c::ErrorKind::Other,
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                Self::InvalidWriteBufferLength => embedded_hal_1::i2c::ErrorKind::Other,
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                Self::AddressOutOfRange(_) => embedded_hal_1::i2c::ErrorKind::Other,
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                Self::AddressReserved(_) => embedded_hal_1::i2c::ErrorKind::Other,
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            }
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        }
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    }
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