Allow upgrading a blocking uart to a BufferedUart, and implement blocking serial traits for BufferedUart
This commit is contained in:
Mathias
parent
055597063f
commit
bce1ce7dcb
@ -28,30 +28,23 @@ impl State {
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}
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pub struct BufferedUart<'d, T: Instance> {
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rx: BufferedUartRx<'d, T>,
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tx: BufferedUartTx<'d, T>,
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pub(crate) rx: BufferedUartRx<'d, T>,
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pub(crate) tx: BufferedUartTx<'d, T>,
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}
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pub struct BufferedUartRx<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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pub(crate) phantom: PhantomData<&'d mut T>,
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}
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pub struct BufferedUartTx<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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pub(crate) phantom: PhantomData<&'d mut T>,
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}
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fn init<'d, T: Instance + 'd>(
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pub(crate) fn init_buffers<'d, T: Instance + 'd>(
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irq: PeripheralRef<'d, T::Interrupt>,
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tx: Option<PeripheralRef<'d, AnyPin>>,
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rx: Option<PeripheralRef<'d, AnyPin>>,
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rts: Option<PeripheralRef<'d, AnyPin>>,
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cts: Option<PeripheralRef<'d, AnyPin>>,
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tx_buffer: &'d mut [u8],
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rx_buffer: &'d mut [u8],
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config: Config,
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) {
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super::Uart::<'d, T, Async>::init(tx, rx, rts, cts, config);
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let state = T::state();
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let len = tx_buffer.len();
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unsafe { state.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
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@ -69,7 +62,13 @@ fn init<'d, T: Instance + 'd>(
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// we clear it after it happens. The downside is that the we manually have
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// to pend the ISR when we want data transmission to start.
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let regs = T::regs();
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unsafe { regs.uartimsc().write_set(|w| w.set_txim(true)) };
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unsafe {
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regs.uartimsc().write_set(|w| {
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w.set_rxim(true);
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w.set_rtim(true);
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w.set_txim(true);
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});
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};
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irq.set_handler(on_interrupt::<T>);
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irq.unpend();
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@ -87,16 +86,10 @@ impl<'d, T: Instance> BufferedUart<'d, T> {
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config: Config,
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) -> Self {
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into_ref!(irq, tx, rx);
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init::<T>(
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irq,
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Some(tx.map_into()),
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Some(rx.map_into()),
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None,
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None,
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tx_buffer,
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rx_buffer,
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config,
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);
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super::Uart::<'d, T, Async>::init(Some(tx.map_into()), Some(rx.map_into()), None, None, config);
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init_buffers::<T>(irq, tx_buffer, rx_buffer);
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Self {
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rx: BufferedUartRx { phantom: PhantomData },
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tx: BufferedUartTx { phantom: PhantomData },
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@ -115,22 +108,34 @@ impl<'d, T: Instance> BufferedUart<'d, T> {
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config: Config,
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) -> Self {
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into_ref!(irq, tx, rx, cts, rts);
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init::<T>(
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irq,
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super::Uart::<'d, T, Async>::init(
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Some(tx.map_into()),
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Some(rx.map_into()),
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Some(rts.map_into()),
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Some(cts.map_into()),
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tx_buffer,
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rx_buffer,
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config,
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);
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init_buffers::<T>(irq, tx_buffer, rx_buffer);
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Self {
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rx: BufferedUartRx { phantom: PhantomData },
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tx: BufferedUartTx { phantom: PhantomData },
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}
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}
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pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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self.tx.blocking_write(buffer)
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}
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pub fn blocking_flush(&mut self) -> Result<(), Error> {
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self.tx.blocking_flush()
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}
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pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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self.rx.blocking_read(buffer)
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}
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pub fn split(self) -> (BufferedUartRx<'d, T>, BufferedUartTx<'d, T>) {
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(self.rx, self.tx)
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}
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@ -145,7 +150,10 @@ impl<'d, T: Instance> BufferedUartRx<'d, T> {
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config: Config,
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) -> Self {
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into_ref!(irq, rx);
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init::<T>(irq, None, Some(rx.map_into()), None, None, &mut [], rx_buffer, config);
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super::Uart::<'d, T, Async>::init(None, Some(rx.map_into()), None, None, config);
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init_buffers::<T>(irq, &mut [], rx_buffer);
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Self { phantom: PhantomData }
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}
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@ -158,16 +166,10 @@ impl<'d, T: Instance> BufferedUartRx<'d, T> {
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config: Config,
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) -> Self {
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into_ref!(irq, rx, rts);
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init::<T>(
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irq,
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None,
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Some(rx.map_into()),
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Some(rts.map_into()),
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None,
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&mut [],
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rx_buffer,
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config,
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);
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super::Uart::<'d, T, Async>::init(None, Some(rx.map_into()), Some(rts.map_into()), None, config);
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init_buffers::<T>(irq, &mut [], rx_buffer);
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Self { phantom: PhantomData }
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}
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@ -199,6 +201,32 @@ impl<'d, T: Instance> BufferedUartRx<'d, T> {
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})
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}
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pub fn blocking_read(&mut self, buf: &mut [u8]) -> Result<(), Error> {
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loop {
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let state = T::state();
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let mut rx_reader = unsafe { state.rx_buf.reader() };
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let n = rx_reader.pop(|data| {
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let n = data.len().min(buf.len());
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buf[..n].copy_from_slice(&data[..n]);
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n
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});
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if n > 0 {
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// (Re-)Enable the interrupt to receive more data in case it was
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// disabled because the buffer was full.
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let regs = T::regs();
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unsafe {
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regs.uartimsc().write_set(|w| {
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w.set_rxim(true);
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w.set_rtim(true);
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});
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}
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return Ok(());
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}
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}
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}
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fn fill_buf<'a>() -> impl Future<Output = Result<&'a [u8], Error>> {
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poll_fn(move |cx| {
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let state = T::state();
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@ -240,7 +268,10 @@ impl<'d, T: Instance> BufferedUartTx<'d, T> {
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config: Config,
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) -> Self {
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into_ref!(irq, tx);
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init::<T>(irq, Some(tx.map_into()), None, None, None, tx_buffer, &mut [], config);
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super::Uart::<'d, T, Async>::init(Some(tx.map_into()), None, None, None, config);
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init_buffers::<T>(irq, tx_buffer, &mut []);
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Self { phantom: PhantomData }
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}
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@ -253,16 +284,10 @@ impl<'d, T: Instance> BufferedUartTx<'d, T> {
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config: Config,
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) -> Self {
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into_ref!(irq, tx, cts);
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init::<T>(
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irq,
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Some(tx.map_into()),
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None,
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None,
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Some(cts.map_into()),
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tx_buffer,
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&mut [],
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config,
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);
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super::Uart::<'d, T, Async>::init(Some(tx.map_into()), None, None, Some(cts.map_into()), config);
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init_buffers::<T>(irq, tx_buffer, &mut []);
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Self { phantom: PhantomData }
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}
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@ -300,6 +325,36 @@ impl<'d, T: Instance> BufferedUartTx<'d, T> {
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Poll::Ready(Ok(()))
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})
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}
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pub fn blocking_write(&mut self, buf: &[u8]) -> Result<(), Error> {
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loop {
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let state = T::state();
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let mut tx_writer = unsafe { state.tx_buf.writer() };
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let n = tx_writer.push(|data| {
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let n = data.len().min(buf.len());
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data[..n].copy_from_slice(&buf[..n]);
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n
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});
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if n != 0 {
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// The TX interrupt only triggers when the there was data in the
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// FIFO and the number of bytes drops below a threshold. When the
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// FIFO was empty we have to manually pend the interrupt to shovel
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// TX data from the buffer into the FIFO.
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unsafe { T::Interrupt::steal() }.pend();
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return Ok(());
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}
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}
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}
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pub fn blocking_flush(&mut self) -> Result<(), Error> {
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loop {
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let state = T::state();
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if state.tx_buf.is_empty() {
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return Ok(());
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}
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}
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}
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}
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impl<'d, T: Instance> Drop for BufferedUartRx<'d, T> {
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@ -477,3 +532,190 @@ impl<'d, T: Instance + 'd> embedded_io::asynch::Write for BufferedUartTx<'d, T>
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Self::flush().await
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}
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}
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mod eh02 {
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use super::*;
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impl<'d, T: Instance> embedded_hal_02::serial::Read<u8> for BufferedUartRx<'d, T> {
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type Error = Error;
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fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
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let r = T::regs();
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unsafe {
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if r.uartfr().read().rxfe() {
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return Err(nb::Error::WouldBlock);
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}
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let dr = r.uartdr().read();
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if dr.oe() {
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Err(nb::Error::Other(Error::Overrun))
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} else if dr.be() {
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Err(nb::Error::Other(Error::Break))
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} else if dr.pe() {
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Err(nb::Error::Other(Error::Parity))
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} else if dr.fe() {
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Err(nb::Error::Other(Error::Framing))
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} else {
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Ok(dr.data())
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}
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}
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}
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}
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impl<'d, T: Instance> embedded_hal_02::blocking::serial::Write<u8> for BufferedUartTx<'d, T> {
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type Error = Error;
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fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
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self.blocking_write(buffer)
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}
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fn bflush(&mut self) -> Result<(), Self::Error> {
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self.blocking_flush()
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}
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}
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impl<'d, T: Instance> embedded_hal_02::serial::Read<u8> for BufferedUart<'d, T> {
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type Error = Error;
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fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
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embedded_hal_02::serial::Read::read(&mut self.rx)
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}
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}
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impl<'d, T: Instance> embedded_hal_02::blocking::serial::Write<u8> for BufferedUart<'d, T> {
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type Error = Error;
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fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
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self.blocking_write(buffer)
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}
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fn bflush(&mut self) -> Result<(), Self::Error> {
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self.blocking_flush()
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}
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}
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}
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#[cfg(feature = "unstable-traits")]
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mod eh1 {
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use super::*;
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impl<'d, T: Instance> embedded_hal_1::serial::ErrorType for BufferedUart<'d, T> {
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type Error = Error;
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}
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impl<'d, T: Instance> embedded_hal_1::serial::ErrorType for BufferedUartTx<'d, T> {
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type Error = Error;
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}
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impl<'d, T: Instance> embedded_hal_1::serial::ErrorType for BufferedUartRx<'d, T> {
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type Error = Error;
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}
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impl<'d, T: Instance> embedded_hal_nb::serial::Read for BufferedUartRx<'d, T> {
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fn read(&mut self) -> nb::Result<u8, Self::Error> {
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embedded_hal_02::serial::Read::read(self)
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}
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}
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impl<'d, T: Instance> embedded_hal_1::serial::Write for BufferedUartTx<'d, T> {
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fn write(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
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self.blocking_write(buffer)
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}
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fn flush(&mut self) -> Result<(), Self::Error> {
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self.blocking_flush()
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}
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}
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impl<'d, T: Instance> embedded_hal_nb::serial::Write for BufferedUartTx<'d, T> {
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fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
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self.blocking_write(&[char]).map_err(nb::Error::Other)
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}
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fn flush(&mut self) -> nb::Result<(), Self::Error> {
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self.blocking_flush().map_err(nb::Error::Other)
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}
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}
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impl<'d, T: Instance> embedded_hal_nb::serial::Read for BufferedUart<'d, T> {
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fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
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embedded_hal_02::serial::Read::read(&mut self.rx)
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}
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}
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impl<'d, T: Instance> embedded_hal_1::serial::Write for BufferedUart<'d, T> {
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fn write(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
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self.blocking_write(buffer)
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}
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fn flush(&mut self) -> Result<(), Self::Error> {
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self.blocking_flush()
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}
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}
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impl<'d, T: Instance> embedded_hal_nb::serial::Write for BufferedUart<'d, T> {
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fn write(&mut self, char: u8) -> nb::Result<(), Self::Error> {
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self.blocking_write(&[char]).map_err(nb::Error::Other)
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}
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fn flush(&mut self) -> nb::Result<(), Self::Error> {
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self.blocking_flush().map_err(nb::Error::Other)
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}
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}
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}
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#[cfg(all(
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feature = "unstable-traits",
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feature = "nightly",
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feature = "_todo_embedded_hal_serial"
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))]
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mod eha {
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use core::future::Future;
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use super::*;
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impl<'d, T: Instance> embedded_hal_async::serial::Write for BufferedUartTx<'d, T> {
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type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
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fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
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Self::write(buf)
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}
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type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
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fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
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Self::flush()
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}
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}
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impl<'d, T: Instance> embedded_hal_async::serial::Read for BufferedUartRx<'d, T> {
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type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
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fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
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Self::read(buf)
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}
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}
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impl<'d, T: Instance> embedded_hal_async::serial::Write for BufferedUart<'d, T> {
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type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
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fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
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BufferedUartTx::<'d, T>::write(buf)
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}
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type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
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fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
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BufferedUartTx::<'d, T>::flush()
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}
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}
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impl<'d, T: Instance> embedded_hal_async::serial::Read for BufferedUart<'d, T> {
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type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
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fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
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BufferedUartRx::<'d, T>::read(buf)
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}
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}
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}
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@ -1,11 +1,12 @@
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use core::marker::PhantomData;
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use embassy_cortex_m::interrupt::InterruptExt;
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use embassy_hal_common::{into_ref, PeripheralRef};
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use crate::dma::{AnyChannel, Channel};
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use crate::gpio::sealed::Pin;
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use crate::gpio::AnyPin;
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use crate::{pac, peripherals, Peripheral};
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use crate::{pac, peripherals, Peripheral, RegExt};
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#[cfg(feature = "nightly")]
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mod buffered;
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@ -135,6 +136,21 @@ impl<'d, T: Instance, M: Mode> UartTx<'d, T, M> {
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}
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}
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impl<'d, T: Instance> UartTx<'d, T, Blocking> {
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#[cfg(feature = "nightly")]
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pub fn into_buffered(
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self,
|
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irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
tx_buffer: &'d mut [u8],
|
||||
) -> BufferedUartTx<'d, T> {
|
||||
into_ref!(irq);
|
||||
|
||||
buffered::init_buffers::<T>(irq, tx_buffer, &mut []);
|
||||
|
||||
BufferedUartTx { phantom: PhantomData }
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> UartTx<'d, T, Async> {
|
||||
pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
|
||||
let ch = self.tx_dma.as_mut().unwrap();
|
||||
@ -200,6 +216,21 @@ impl<'d, T: Instance, M: Mode> UartRx<'d, T, M> {
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> UartRx<'d, T, Blocking> {
|
||||
#[cfg(feature = "nightly")]
|
||||
pub fn into_buffered(
|
||||
self,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
rx_buffer: &'d mut [u8],
|
||||
) -> BufferedUartRx<'d, T> {
|
||||
into_ref!(irq);
|
||||
|
||||
buffered::init_buffers::<T>(irq, &mut [], rx_buffer);
|
||||
|
||||
BufferedUartRx { phantom: PhantomData }
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> UartRx<'d, T, Async> {
|
||||
pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
|
||||
let ch = self.rx_dma.as_mut().unwrap();
|
||||
@ -249,6 +280,23 @@ impl<'d, T: Instance> Uart<'d, T, Blocking> {
|
||||
config,
|
||||
)
|
||||
}
|
||||
|
||||
#[cfg(feature = "nightly")]
|
||||
pub fn into_buffered(
|
||||
self,
|
||||
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
||||
tx_buffer: &'d mut [u8],
|
||||
rx_buffer: &'d mut [u8],
|
||||
) -> BufferedUart<'d, T> {
|
||||
into_ref!(irq);
|
||||
|
||||
buffered::init_buffers::<T>(irq, tx_buffer, rx_buffer);
|
||||
|
||||
BufferedUart {
|
||||
rx: BufferedUartRx { phantom: PhantomData },
|
||||
tx: BufferedUartTx { phantom: PhantomData },
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> Uart<'d, T, Async> {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user