Add ADC
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				@ -10,7 +10,7 @@
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#[cfg_attr(adc_v1, path = "v1.rs")]
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					#[cfg_attr(adc_v1, path = "v1.rs")]
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#[cfg_attr(adc_l0, path = "v1.rs")]
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					#[cfg_attr(adc_l0, path = "v1.rs")]
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#[cfg_attr(adc_v2, path = "v2.rs")]
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					#[cfg_attr(adc_v2, path = "v2.rs")]
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#[cfg_attr(any(adc_v3, adc_g0, adc_h5), path = "v3.rs")]
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					#[cfg_attr(any(adc_v3, adc_g0, adc_h5, adc_u0), path = "v3.rs")]
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#[cfg_attr(adc_v4, path = "v4.rs")]
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					#[cfg_attr(adc_v4, path = "v4.rs")]
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#[cfg_attr(adc_g4, path = "g4.rs")]
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					#[cfg_attr(adc_g4, path = "g4.rs")]
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mod _version;
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					mod _version;
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@ -91,6 +91,7 @@ pub(crate) fn blocking_delay_us(us: u32) {
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    adc_f3,
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					    adc_f3,
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    adc_f3_v1_1,
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					    adc_f3_v1_1,
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    adc_g0,
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					    adc_g0,
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					    adc_u0,
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    adc_h5
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					    adc_h5
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)))]
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					)))]
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#[allow(private_bounds)]
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					#[allow(private_bounds)]
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@ -109,6 +110,7 @@ pub trait Instance: SealedInstance + crate::Peripheral<P = Self> {
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    adc_f3,
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					    adc_f3,
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    adc_f3_v1_1,
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					    adc_f3_v1_1,
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    adc_g0,
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					    adc_g0,
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					    adc_u0,
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    adc_h5
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					    adc_h5
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))]
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					))]
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#[allow(private_bounds)]
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					#[allow(private_bounds)]
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@ -19,6 +19,8 @@ impl<T: Instance> super::SealedAdcPin<T> for VrefInt {
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                let val = 13;
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					                let val = 13;
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            } else if #[cfg(adc_h5)] {
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					            } else if #[cfg(adc_h5)] {
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                let val = 17;
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					                let val = 17;
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					            } else if #[cfg(adc_u0)] {
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					                let val = 12;
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            } else {
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					            } else {
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                let val = 0;
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					                let val = 0;
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            }
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					            }
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@ -36,6 +38,8 @@ impl<T: Instance> super::SealedAdcPin<T> for Temperature {
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                let val = 12;
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					                let val = 12;
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            } else if #[cfg(adc_h5)] {
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					            } else if #[cfg(adc_h5)] {
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                let val = 16;
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					                let val = 16;
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					            } else if #[cfg(adc_u0)] {
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					                let val = 11;
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            } else {
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					            } else {
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                let val = 17;
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					                let val = 17;
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            }
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					            }
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@ -53,6 +57,8 @@ impl<T: Instance> super::SealedAdcPin<T> for Vbat {
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                let val = 14;
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					                let val = 14;
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            } else if #[cfg(adc_h5)] {
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					            } else if #[cfg(adc_h5)] {
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                let val = 2;
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					                let val = 2;
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					            } else if #[cfg(adc_h5)] {
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					                let val = 13;
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            } else {
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					            } else {
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                let val = 18;
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					                let val = 18;
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            }
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					            }
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@ -73,17 +79,29 @@ cfg_if! {
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    }
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					    }
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}
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					}
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					cfg_if! {
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					    if #[cfg(adc_u0)] {
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					        pub struct DacOut;
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					        impl<T: Instance> AdcPin<T> for DacOut {}
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					        impl<T: Instance> super::SealedAdcPin<T> for DacOut {
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					            fn channel(&self) -> u8 {
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					                19
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					            }
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					        }
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					    }
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					}
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impl<'d, T: Instance> Adc<'d, T> {
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					impl<'d, T: Instance> Adc<'d, T> {
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    pub fn new(adc: impl Peripheral<P = T> + 'd) -> Self {
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					    pub fn new(adc: impl Peripheral<P = T> + 'd) -> Self {
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        into_ref!(adc);
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					        into_ref!(adc);
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        T::enable_and_reset();
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					        T::enable_and_reset();
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        T::regs().cr().modify(|reg| {
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					        T::regs().cr().modify(|reg| {
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            #[cfg(not(adc_g0))]
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					            #[cfg(not(any(adc_g0, adc_u0)))]
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            reg.set_deeppwd(false);
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					            reg.set_deeppwd(false);
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            reg.set_advregen(true);
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					            reg.set_advregen(true);
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        });
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					        });
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        #[cfg(adc_g0)]
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					        #[cfg(any(adc_g0, adc_u0))]
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        T::regs().cfgr1().modify(|reg| {
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					        T::regs().cfgr1().modify(|reg| {
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            reg.set_chselrmod(false);
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					            reg.set_chselrmod(false);
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        });
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					        });
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@ -107,11 +125,11 @@ impl<'d, T: Instance> Adc<'d, T> {
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    }
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					    }
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    pub fn enable_vrefint(&self) -> VrefInt {
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					    pub fn enable_vrefint(&self) -> VrefInt {
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        #[cfg(not(adc_g0))]
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					        #[cfg(not(any(adc_g0, adc_u0)))]
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        T::common_regs().ccr().modify(|reg| {
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					        T::common_regs().ccr().modify(|reg| {
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            reg.set_vrefen(true);
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					            reg.set_vrefen(true);
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        });
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					        });
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        #[cfg(adc_g0)]
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					        #[cfg(any(adc_g0, adc_u0))]
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        T::regs().ccr().modify(|reg| {
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					        T::regs().ccr().modify(|reg| {
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            reg.set_vrefen(true);
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					            reg.set_vrefen(true);
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        });
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					        });
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@ -125,7 +143,7 @@ impl<'d, T: Instance> Adc<'d, T> {
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    pub fn enable_temperature(&self) -> Temperature {
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					    pub fn enable_temperature(&self) -> Temperature {
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        cfg_if! {
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					        cfg_if! {
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            if #[cfg(adc_g0)] {
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					            if #[cfg(any(adc_g0, adc_u0))] {
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                T::regs().ccr().modify(|reg| {
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					                T::regs().ccr().modify(|reg| {
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                    reg.set_tsen(true);
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					                    reg.set_tsen(true);
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                });
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					                });
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@ -145,7 +163,7 @@ impl<'d, T: Instance> Adc<'d, T> {
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    pub fn enable_vbat(&self) -> Vbat {
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					    pub fn enable_vbat(&self) -> Vbat {
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        cfg_if! {
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					        cfg_if! {
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            if #[cfg(adc_g0)] {
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					            if #[cfg(any(adc_g0, adc_u0))] {
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                T::regs().ccr().modify(|reg| {
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					                T::regs().ccr().modify(|reg| {
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                    reg.set_vbaten(true);
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					                    reg.set_vbaten(true);
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                });
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					                });
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@ -168,9 +186,9 @@ impl<'d, T: Instance> Adc<'d, T> {
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    }
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					    }
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    pub fn set_resolution(&mut self, resolution: Resolution) {
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					    pub fn set_resolution(&mut self, resolution: Resolution) {
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        #[cfg(not(adc_g0))]
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					        #[cfg(not(any(adc_g0, adc_u0)))]
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        T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
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					        T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
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        #[cfg(adc_g0)]
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					        #[cfg(any(adc_g0, adc_u0))]
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        T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
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					        T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
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    }
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					    }
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@ -231,9 +249,9 @@ impl<'d, T: Instance> Adc<'d, T> {
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        Self::set_channel_sample_time(pin.channel(), self.sample_time);
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					        Self::set_channel_sample_time(pin.channel(), self.sample_time);
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        // Select channel
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					        // Select channel
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        #[cfg(not(adc_g0))]
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					        #[cfg(not(any(adc_g0, adc_u0)))]
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        T::regs().sqr1().write(|reg| reg.set_sq(0, pin.channel()));
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					        T::regs().sqr1().write(|reg| reg.set_sq(0, pin.channel()));
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        #[cfg(adc_g0)]
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					        #[cfg(any(adc_g0, adc_u0))]
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        T::regs().chselr().write(|reg| reg.set_chsel(1 << pin.channel()));
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					        T::regs().chselr().write(|reg| reg.set_chsel(1 << pin.channel()));
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        // Some models are affected by an erratum:
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					        // Some models are affected by an erratum:
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@ -261,7 +279,7 @@ impl<'d, T: Instance> Adc<'d, T> {
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    fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) {
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					    fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) {
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        cfg_if! {
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					        cfg_if! {
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            if #[cfg(adc_g0)] {
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					            if #[cfg(any(adc_g0, adc_u0))] {
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                T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
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					                T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
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            } else if #[cfg(adc_h5)] {
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					            } else if #[cfg(adc_h5)] {
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                match _ch {
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					                match _ch {
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@ -26,8 +26,6 @@ fn main() -> ! {
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    loop {
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					    loop {
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        let v = adc.read(&mut channel);
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					        let v = adc.read(&mut channel);
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        info!("--> {}", v);
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					        info!("--> {}", v);
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        let v = adc.read(&mut temp);
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					        embassy_time::block_for(Duration::from_millis(200));
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        info!("Temp: --> {}", v);
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        embassy_time::block_for(Duration::from_millis(1000));
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    }
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					    }
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}
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					}
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