Fix txonly/rxonly data pin dir, _from_ram and doc
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				@ -78,7 +78,7 @@ impl<'d, T: Instance> Spis<'d, T> {
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        irq: impl Peripheral<P = T::Interrupt> + 'd,
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					        irq: impl Peripheral<P = T::Interrupt> + 'd,
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        cs: impl Peripheral<P = impl GpioPin> + 'd,
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					        cs: impl Peripheral<P = impl GpioPin> + 'd,
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        sck: impl Peripheral<P = impl GpioPin> + 'd,
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					        sck: impl Peripheral<P = impl GpioPin> + 'd,
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        mosi: impl Peripheral<P = impl GpioPin> + 'd,
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					        miso: impl Peripheral<P = impl GpioPin> + 'd,
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        config: Config,
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					        config: Config,
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    ) -> Self {
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					    ) -> Self {
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        into_ref!(cs, sck, mosi);
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					        into_ref!(cs, sck, mosi);
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@ -87,8 +87,8 @@ impl<'d, T: Instance> Spis<'d, T> {
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            irq,
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					            irq,
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            cs.map_into(),
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					            cs.map_into(),
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            sck.map_into(),
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					            sck.map_into(),
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					            Some(miso.map_into()),
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            None,
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					            None,
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            Some(mosi.map_into()),
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            config,
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					            config,
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        )
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					        )
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    }
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					    }
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@ -98,7 +98,7 @@ impl<'d, T: Instance> Spis<'d, T> {
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        irq: impl Peripheral<P = T::Interrupt> + 'd,
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					        irq: impl Peripheral<P = T::Interrupt> + 'd,
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        cs: impl Peripheral<P = impl GpioPin> + 'd,
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					        cs: impl Peripheral<P = impl GpioPin> + 'd,
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        sck: impl Peripheral<P = impl GpioPin> + 'd,
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					        sck: impl Peripheral<P = impl GpioPin> + 'd,
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        miso: impl Peripheral<P = impl GpioPin> + 'd,
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					        mosi: impl Peripheral<P = impl GpioPin> + 'd,
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        config: Config,
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					        config: Config,
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    ) -> Self {
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					    ) -> Self {
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        into_ref!(cs, sck, miso);
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					        into_ref!(cs, sck, miso);
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@ -107,8 +107,8 @@ impl<'d, T: Instance> Spis<'d, T> {
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            irq,
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					            irq,
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            cs.map_into(),
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					            cs.map_into(),
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            sck.map_into(),
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					            sck.map_into(),
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            Some(miso.map_into()),
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            None,
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					            None,
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					            Some(mosi.map_into()),
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            config,
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					            config,
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        )
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					        )
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    }
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					    }
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@ -355,7 +355,7 @@ impl<'d, T: Instance> Spis<'d, T> {
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        }
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					        }
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    }
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					    }
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    /// Reads data from the SPI bus without sending anything. Blocks until the buffer has been filled.
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					    /// Reads data from the SPI bus without sending anything. Blocks until `cs` is deasserted.
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    /// Returns number of bytes read.
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					    /// Returns number of bytes read.
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    pub fn blocking_read(&mut self, data: &mut [u8]) -> Result<usize, Error> {
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					    pub fn blocking_read(&mut self, data: &mut [u8]) -> Result<usize, Error> {
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        self.blocking_inner(data, &[]).map(|n| n.0)
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					        self.blocking_inner(data, &[]).map(|n| n.0)
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@ -371,7 +371,7 @@ impl<'d, T: Instance> Spis<'d, T> {
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    /// Same as [`blocking_transfer`](Spis::blocking_transfer) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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					    /// Same as [`blocking_transfer`](Spis::blocking_transfer) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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    /// Returns number of bytes transferred `(n_rx, n_tx)`.
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					    /// Returns number of bytes transferred `(n_rx, n_tx)`.
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    pub fn blocking_transfer_from_ram(&mut self, read: &mut [u8], write: &[u8]) -> Result<(usize, usize), Error> {
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					    pub fn blocking_transfer_from_ram(&mut self, read: &mut [u8], write: &[u8]) -> Result<(usize, usize), Error> {
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        self.blocking_inner(read, write)
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					        self.blocking_inner_from_ram(read, write)
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    }
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					    }
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    /// Simultaneously sends and receives data.
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					    /// Simultaneously sends and receives data.
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@ -391,7 +391,7 @@ impl<'d, T: Instance> Spis<'d, T> {
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    /// Same as [`blocking_write`](Spis::blocking_write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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					    /// Same as [`blocking_write`](Spis::blocking_write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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    /// Returns number of bytes written.
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					    /// Returns number of bytes written.
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    pub fn blocking_write_from_ram(&mut self, data: &[u8]) -> Result<usize, Error> {
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					    pub fn blocking_write_from_ram(&mut self, data: &[u8]) -> Result<usize, Error> {
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        self.blocking_inner(&mut [], data).map(|n| n.1)
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					        self.blocking_inner_from_ram(&mut [], data).map(|n| n.1)
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    }
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					    }
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    /// Reads data from the SPI bus without sending anything.
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					    /// Reads data from the SPI bus without sending anything.
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