Merge pull request #4127 from skoe/adjust-opamp-less-emums
Update opamp code to current stm32-metapac
This commit is contained in:
commit
a687fb20f6
@ -73,7 +73,7 @@ rand_core = "0.6.3"
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sdio-host = "0.9.0"
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sdio-host = "0.9.0"
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critical-section = "1.1"
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critical-section = "1.1"
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#stm32-metapac = { version = "16" }
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#stm32-metapac = { version = "16" }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-380f03cb71f43a242adc45e83607a380ffe0447b" }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-9385c0824aff194913a2eab3c957791d0de06771" }
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vcell = "0.1.3"
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vcell = "0.1.3"
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nb = "1.0.0"
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nb = "1.0.0"
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@ -102,7 +102,7 @@ proc-macro2 = "1.0.36"
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quote = "1.0.15"
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quote = "1.0.15"
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#stm32-metapac = { version = "16", default-features = false, features = ["metadata"]}
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#stm32-metapac = { version = "16", default-features = false, features = ["metadata"]}
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-380f03cb71f43a242adc45e83607a380ffe0447b", default-features = false, features = ["metadata"] }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-9385c0824aff194913a2eab3c957791d0de06771", default-features = false, features = ["metadata"] }
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[features]
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[features]
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default = ["rt"]
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default = ["rt"]
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@ -11,7 +11,7 @@
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#[cfg_attr(adc_v1, path = "v1.rs")]
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#[cfg_attr(adc_v1, path = "v1.rs")]
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#[cfg_attr(adc_l0, path = "v1.rs")]
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#[cfg_attr(adc_l0, path = "v1.rs")]
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#[cfg_attr(adc_v2, path = "v2.rs")]
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#[cfg_attr(adc_v2, path = "v2.rs")]
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#[cfg_attr(any(adc_v3, adc_g0, adc_h5, adc_u0), path = "v3.rs")]
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#[cfg_attr(any(adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0), path = "v3.rs")]
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#[cfg_attr(any(adc_v4, adc_u5), path = "v4.rs")]
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#[cfg_attr(any(adc_v4, adc_u5), path = "v4.rs")]
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#[cfg_attr(adc_g4, path = "g4.rs")]
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#[cfg_attr(adc_g4, path = "g4.rs")]
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#[cfg_attr(adc_c0, path = "c0.rs")]
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#[cfg_attr(adc_c0, path = "c0.rs")]
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@ -108,6 +108,7 @@ pub(crate) fn blocking_delay_us(us: u32) {
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adc_g0,
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adc_g0,
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adc_u0,
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adc_u0,
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adc_h5,
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adc_h5,
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adc_h7rs,
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adc_u5,
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adc_u5,
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adc_c0
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adc_c0
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)))]
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)))]
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@ -129,6 +130,7 @@ pub trait Instance: SealedInstance + crate::PeripheralType {
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adc_g0,
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adc_g0,
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adc_u0,
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adc_u0,
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adc_h5,
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adc_h5,
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adc_h7rs,
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adc_u5,
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adc_u5,
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adc_c0
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adc_c0
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))]
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))]
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@ -19,7 +19,7 @@ impl<T: Instance> SealedAdcChannel<T> for VrefInt {
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cfg_if! {
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cfg_if! {
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if #[cfg(adc_g0)] {
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if #[cfg(adc_g0)] {
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let val = 13;
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let val = 13;
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} else if #[cfg(adc_h5)] {
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} else if #[cfg(any(adc_h5, adc_h7rs))] {
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let val = 17;
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let val = 17;
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} else if #[cfg(adc_u0)] {
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} else if #[cfg(adc_u0)] {
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let val = 12;
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let val = 12;
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@ -38,7 +38,7 @@ impl<T: Instance> SealedAdcChannel<T> for Temperature {
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cfg_if! {
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cfg_if! {
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if #[cfg(adc_g0)] {
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if #[cfg(adc_g0)] {
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let val = 12;
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let val = 12;
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} else if #[cfg(adc_h5)] {
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} else if #[cfg(any(adc_h5, adc_h7rs))] {
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let val = 16;
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let val = 16;
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} else if #[cfg(adc_u0)] {
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} else if #[cfg(adc_u0)] {
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let val = 11;
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let val = 11;
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@ -57,9 +57,9 @@ impl<T: Instance> SealedAdcChannel<T> for Vbat {
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cfg_if! {
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cfg_if! {
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if #[cfg(adc_g0)] {
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if #[cfg(adc_g0)] {
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let val = 14;
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let val = 14;
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} else if #[cfg(adc_h5)] {
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} else if #[cfg(any(adc_h5, adc_h7rs))] {
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let val = 2;
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let val = 2;
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} else if #[cfg(adc_h5)] {
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} else if #[cfg(any(adc_h5, adc_h7rs))] {
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let val = 13;
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let val = 13;
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} else {
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} else {
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let val = 18;
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let val = 18;
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@ -70,7 +70,7 @@ impl<T: Instance> SealedAdcChannel<T> for Vbat {
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}
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}
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cfg_if! {
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cfg_if! {
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if #[cfg(adc_h5)] {
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if #[cfg(any(adc_h5, adc_h7rs))] {
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pub struct VddCore;
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pub struct VddCore;
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impl<T: Instance> AdcChannel<T> for VddCore {}
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impl<T: Instance> AdcChannel<T> for VddCore {}
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impl<T: Instance> super::SealedAdcChannel<T> for VddCore {
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impl<T: Instance> super::SealedAdcChannel<T> for VddCore {
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@ -171,7 +171,7 @@ impl<'d, T: Instance> Adc<'d, T> {
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T::regs().ccr().modify(|reg| {
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T::regs().ccr().modify(|reg| {
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reg.set_tsen(true);
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reg.set_tsen(true);
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});
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});
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} else if #[cfg(adc_h5)] {
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} else if #[cfg(any(adc_h5, adc_h7rs))] {
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T::common_regs().ccr().modify(|reg| {
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T::common_regs().ccr().modify(|reg| {
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reg.set_tsen(true);
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reg.set_tsen(true);
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});
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});
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@ -191,7 +191,7 @@ impl<'d, T: Instance> Adc<'d, T> {
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T::regs().ccr().modify(|reg| {
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T::regs().ccr().modify(|reg| {
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reg.set_vbaten(true);
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reg.set_vbaten(true);
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});
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});
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} else if #[cfg(adc_h5)] {
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} else if #[cfg(any(adc_h5, adc_h7rs))] {
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T::common_regs().ccr().modify(|reg| {
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T::common_regs().ccr().modify(|reg| {
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reg.set_vbaten(true);
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reg.set_vbaten(true);
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});
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});
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@ -414,7 +414,7 @@ impl<'d, T: Instance> Adc<'d, T> {
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fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
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fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
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// RM0492, RM0481, etc.
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// RM0492, RM0481, etc.
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// "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
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// "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
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#[cfg(adc_h5)]
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#[cfg(any(adc_h5, adc_h7rs))]
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if channel.channel() == 0 {
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if channel.channel() == 0 {
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T::regs().or().modify(|reg| reg.set_op0(true));
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T::regs().or().modify(|reg| reg.set_op0(true));
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}
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}
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@ -447,7 +447,7 @@ impl<'d, T: Instance> Adc<'d, T> {
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// RM0492, RM0481, etc.
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// RM0492, RM0481, etc.
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// "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
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// "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
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#[cfg(adc_h5)]
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#[cfg(any(adc_h5, adc_h7rs))]
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if channel.channel() == 0 {
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if channel.channel() == 0 {
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T::regs().or().modify(|reg| reg.set_op0(false));
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T::regs().or().modify(|reg| reg.set_op0(false));
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}
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}
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@ -475,7 +475,7 @@ impl<'d, T: Instance> Adc<'d, T> {
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if #[cfg(any(adc_g0, adc_u0))] {
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if #[cfg(any(adc_g0, adc_u0))] {
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// On G0 and U6 all channels use the same sampling time.
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// On G0 and U6 all channels use the same sampling time.
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T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
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T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
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} else if #[cfg(adc_h5)] {
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} else if #[cfg(any(adc_h5, adc_h7rs))] {
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match _ch {
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match _ch {
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0..=9 => T::regs().smpr1().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
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0..=9 => T::regs().smpr1().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
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_ => T::regs().smpr2().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
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_ => T::regs().smpr2().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
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@ -37,22 +37,12 @@ enum OpAmpDifferentialPair {
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/// Speed
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/// Speed
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#[allow(missing_docs)]
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#[allow(missing_docs)]
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#[derive(Clone, Copy)]
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#[derive(Clone, Copy, PartialEq)]
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pub enum OpAmpSpeed {
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pub enum OpAmpSpeed {
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Normal,
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Normal,
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HighSpeed,
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HighSpeed,
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}
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}
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#[cfg(opamp_g4)]
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impl From<OpAmpSpeed> for crate::pac::opamp::vals::Opahsm {
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fn from(v: OpAmpSpeed) -> Self {
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match v {
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OpAmpSpeed::Normal => crate::pac::opamp::vals::Opahsm::NORMAL,
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OpAmpSpeed::HighSpeed => crate::pac::opamp::vals::Opahsm::HIGH_SPEED,
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}
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}
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}
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/// OpAmp external outputs, wired to a GPIO pad.
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/// OpAmp external outputs, wired to a GPIO pad.
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///
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///
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/// This struct can also be used as an ADC input.
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/// This struct can also be used as an ADC input.
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@ -80,7 +70,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
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pub fn new(opamp: Peri<'d, T>, #[cfg(opamp_g4)] speed: OpAmpSpeed) -> Self {
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pub fn new(opamp: Peri<'d, T>, #[cfg(opamp_g4)] speed: OpAmpSpeed) -> Self {
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#[cfg(opamp_g4)]
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#[cfg(opamp_g4)]
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T::regs().csr().modify(|w| {
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T::regs().csr().modify(|w| {
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w.set_opahsm(speed.into());
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w.set_opahsm(speed == OpAmpSpeed::HighSpeed);
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});
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});
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Self { _inner: opamp }
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Self { _inner: opamp }
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@ -113,7 +103,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
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w.set_vp_sel(VpSel::from_bits(in_pin.channel()));
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w.set_vp_sel(VpSel::from_bits(in_pin.channel()));
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w.set_vm_sel(vm_sel);
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w.set_vm_sel(vm_sel);
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#[cfg(opamp_g4)]
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#[cfg(opamp_g4)]
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w.set_opaintoen(Opaintoen::OUTPUT_PIN);
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w.set_opaintoen(false);
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w.set_opampen(true);
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w.set_opampen(true);
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});
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});
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@ -166,7 +156,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
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w.set_vm_sel(vm_sel);
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w.set_vm_sel(vm_sel);
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w.set_pga_gain(pga_gain);
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w.set_pga_gain(pga_gain);
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#[cfg(opamp_g4)]
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#[cfg(opamp_g4)]
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w.set_opaintoen(Opaintoen::OUTPUT_PIN);
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w.set_opaintoen(false);
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w.set_opampen(true);
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w.set_opampen(true);
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});
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});
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@ -189,7 +179,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
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w.set_vm_sel(VmSel::OUTPUT);
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w.set_vm_sel(VmSel::OUTPUT);
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w.set_vp_sel(VpSel::DAC3_CH1);
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w.set_vp_sel(VpSel::DAC3_CH1);
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w.set_opaintoen(Opaintoen::OUTPUT_PIN);
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w.set_opaintoen(false);
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w.set_opampen(true);
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w.set_opampen(true);
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});
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});
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@ -215,7 +205,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
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w.set_vp_sel(VpSel::from_bits(pin.channel()));
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w.set_vp_sel(VpSel::from_bits(pin.channel()));
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w.set_vm_sel(VmSel::OUTPUT);
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w.set_vm_sel(VmSel::OUTPUT);
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#[cfg(opamp_g4)]
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#[cfg(opamp_g4)]
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w.set_opaintoen(Opaintoen::ADCCHANNEL);
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w.set_opaintoen(true);
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w.set_opampen(true);
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w.set_opampen(true);
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});
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});
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@ -251,7 +241,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
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w.set_vp_sel(VpSel::from_bits(pin.channel()));
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w.set_vp_sel(VpSel::from_bits(pin.channel()));
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w.set_vm_sel(VmSel::OUTPUT);
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w.set_vm_sel(VmSel::OUTPUT);
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w.set_pga_gain(pga_gain);
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w.set_pga_gain(pga_gain);
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w.set_opaintoen(Opaintoen::ADCCHANNEL);
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w.set_opaintoen(true);
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w.set_opampen(true);
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w.set_opampen(true);
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});
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});
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@ -278,7 +268,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
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use crate::pac::opamp::vals::*;
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use crate::pac::opamp::vals::*;
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w.set_vp_sel(VpSel::DAC3_CH1); // Actually DAC3_CHx
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w.set_vp_sel(VpSel::DAC3_CH1); // Actually DAC3_CHx
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w.set_vm_sel(VmSel::from_bits(m_pin.channel()));
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w.set_vm_sel(VmSel::from_bits(m_pin.channel()));
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w.set_opaintoen(Opaintoen::ADCCHANNEL);
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w.set_opaintoen(true);
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w.set_opampen(true);
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w.set_opampen(true);
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});
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});
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@ -308,7 +298,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
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use crate::pac::opamp::vals::*;
|
use crate::pac::opamp::vals::*;
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w.set_vp_sel(VpSel::DAC3_CH1); // Actually DAC3_CHx
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w.set_vp_sel(VpSel::DAC3_CH1); // Actually DAC3_CHx
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w.set_vm_sel(VmSel::from_bits(m_pin.channel()));
|
w.set_vm_sel(VmSel::from_bits(m_pin.channel()));
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w.set_opaintoen(Opaintoen::OUTPUT_PIN);
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w.set_opaintoen(false);
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w.set_opampen(true);
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w.set_opampen(true);
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||||||
});
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});
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@ -340,7 +330,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
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use crate::pac::opamp::vals::*;
|
use crate::pac::opamp::vals::*;
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w.set_vp_sel(VpSel::from_bits(p_pin.channel()));
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w.set_vp_sel(VpSel::from_bits(p_pin.channel()));
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w.set_vm_sel(VmSel::from_bits(m_pin.channel()));
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w.set_vm_sel(VmSel::from_bits(m_pin.channel()));
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w.set_opaintoen(Opaintoen::OUTPUT_PIN);
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w.set_opaintoen(false);
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w.set_opampen(true);
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w.set_opampen(true);
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});
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});
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@ -369,7 +359,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
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|||||||
use crate::pac::opamp::vals::*;
|
use crate::pac::opamp::vals::*;
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w.set_vp_sel(VpSel::from_bits(p_pin.channel()));
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w.set_vp_sel(VpSel::from_bits(p_pin.channel()));
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w.set_vm_sel(VmSel::from_bits(m_pin.channel()));
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w.set_vm_sel(VmSel::from_bits(m_pin.channel()));
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w.set_opaintoen(Opaintoen::ADCCHANNEL);
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w.set_opaintoen(true);
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w.set_opampen(true);
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w.set_opampen(true);
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});
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});
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|
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@ -389,17 +379,14 @@ impl<'d, T: Instance> OpAmp<'d, T> {
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T::regs().csr().modify(|w| {
|
T::regs().csr().modify(|w| {
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w.set_opampen(true);
|
w.set_opampen(true);
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w.set_calon(true);
|
w.set_calon(true);
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w.set_usertrim(Usertrim::USER);
|
w.set_usertrim(true);
|
||||||
});
|
});
|
||||||
|
|
||||||
match T::regs().csr().read().opahsm() {
|
if T::regs().csr().read().opahsm() {
|
||||||
Opahsm::NORMAL => {
|
self.calibrate_differential_pair(OpAmpDifferentialPair::P);
|
||||||
self.calibrate_differential_pair(OpAmpDifferentialPair::P);
|
} else {
|
||||||
self.calibrate_differential_pair(OpAmpDifferentialPair::N);
|
self.calibrate_differential_pair(OpAmpDifferentialPair::P);
|
||||||
}
|
self.calibrate_differential_pair(OpAmpDifferentialPair::N);
|
||||||
Opahsm::HIGH_SPEED => {
|
|
||||||
self.calibrate_differential_pair(OpAmpDifferentialPair::P);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
T::regs().csr().modify(|w| {
|
T::regs().csr().modify(|w| {
|
||||||
@ -448,7 +435,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
|
|||||||
// (with a maximum stabilization time remaining below 2 ms in any case) -- RM0440 25.3.7
|
// (with a maximum stabilization time remaining below 2 ms in any case) -- RM0440 25.3.7
|
||||||
blocking_delay_ms(2);
|
blocking_delay_ms(2);
|
||||||
|
|
||||||
if T::regs().csr().read().outcal() == Outcal::LOW {
|
if !T::regs().csr().read().calout() {
|
||||||
if mid == 0 {
|
if mid == 0 {
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user