Add tx_ptr and rx_ptr methods
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				| @ -290,6 +290,29 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { | |||||||
|     } |     } | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
|  | trait RegsExt { | ||||||
|  |     fn tx_ptr<W>(&self) -> *mut W; | ||||||
|  |     fn rx_ptr<W>(&self) -> *mut W; | ||||||
|  | } | ||||||
|  | 
 | ||||||
|  | impl RegsExt for crate::pac::spi::Spi { | ||||||
|  |     fn tx_ptr<W>(&self) -> *mut W { | ||||||
|  |         #[cfg(not(spi_v3))] | ||||||
|  |         let dr = self.dr(); | ||||||
|  |         #[cfg(spi_v3)] | ||||||
|  |         let dr = self.txdr(); | ||||||
|  |         dr.ptr() as *mut W | ||||||
|  |     } | ||||||
|  | 
 | ||||||
|  |     fn rx_ptr<W>(&self) -> *mut W { | ||||||
|  |         #[cfg(not(spi_v3))] | ||||||
|  |         let dr = self.dr(); | ||||||
|  |         #[cfg(spi_v3)] | ||||||
|  |         let dr = self.rxdr(); | ||||||
|  |         dr.ptr() as *mut W | ||||||
|  |     } | ||||||
|  | } | ||||||
|  | 
 | ||||||
| pub(crate) mod sealed { | pub(crate) mod sealed { | ||||||
|     use super::*; |     use super::*; | ||||||
| 
 | 
 | ||||||
|  | |||||||
| @ -2,7 +2,7 @@ | |||||||
| 
 | 
 | ||||||
| use crate::dma::NoDma; | use crate::dma::NoDma; | ||||||
| use crate::gpio::sealed::Pin; | use crate::gpio::sealed::Pin; | ||||||
| use crate::spi::{Error, Instance, RxDmaChannel, TxDmaChannel, WordSize}; | use crate::spi::{Error, Instance, RegsExt, RxDmaChannel, TxDmaChannel, WordSize}; | ||||||
| use core::future::Future; | use core::future::Future; | ||||||
| use core::ptr; | use core::ptr; | ||||||
| use embassy_traits::spi as traits; | use embassy_traits::spi as traits; | ||||||
| @ -42,7 +42,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { | |||||||
|         self.set_word_size(WordSize::EightBit); |         self.set_word_size(WordSize::EightBit); | ||||||
| 
 | 
 | ||||||
|         let request = self.txdma.request(); |         let request = self.txdma.request(); | ||||||
|         let dst = T::regs().dr().ptr() as *mut u8; |         let dst = T::regs().tx_ptr(); | ||||||
|         let f = self.txdma.write(request, write, dst); |         let f = self.txdma.write(request, write, dst); | ||||||
| 
 | 
 | ||||||
|         unsafe { |         unsafe { | ||||||
| @ -77,11 +77,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { | |||||||
|         let clock_byte_count = read.len(); |         let clock_byte_count = read.len(); | ||||||
| 
 | 
 | ||||||
|         let rx_request = self.rxdma.request(); |         let rx_request = self.rxdma.request(); | ||||||
|         let rx_src = T::regs().dr().ptr() as *mut u8; |         let rx_src = T::regs().rx_ptr(); | ||||||
|         let rx_f = self.rxdma.read(rx_request, rx_src, read); |         let rx_f = self.rxdma.read(rx_request, rx_src, read); | ||||||
| 
 | 
 | ||||||
|         let tx_request = self.txdma.request(); |         let tx_request = self.txdma.request(); | ||||||
|         let tx_dst = T::regs().dr().ptr() as *mut u8; |         let tx_dst = T::regs().tx_ptr(); | ||||||
|         let clock_byte = 0x00; |         let clock_byte = 0x00; | ||||||
|         let tx_f = self |         let tx_f = self | ||||||
|             .txdma |             .txdma | ||||||
| @ -130,13 +130,13 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { | |||||||
|         self.set_word_size(WordSize::EightBit); |         self.set_word_size(WordSize::EightBit); | ||||||
| 
 | 
 | ||||||
|         let rx_request = self.rxdma.request(); |         let rx_request = self.rxdma.request(); | ||||||
|         let rx_src = T::regs().dr().ptr() as *mut u8; |         let rx_src = T::regs().rx_ptr(); | ||||||
|         let rx_f = self |         let rx_f = self | ||||||
|             .rxdma |             .rxdma | ||||||
|             .read(rx_request, rx_src, &mut read[0..write.len()]); |             .read(rx_request, rx_src, &mut read[0..write.len()]); | ||||||
| 
 | 
 | ||||||
|         let tx_request = self.txdma.request(); |         let tx_request = self.txdma.request(); | ||||||
|         let tx_dst = T::regs().dr().ptr() as *mut u8; |         let tx_dst = T::regs().tx_ptr(); | ||||||
|         let tx_f = self.txdma.write(tx_request, write, tx_dst); |         let tx_f = self.txdma.write(tx_request, write, tx_dst); | ||||||
| 
 | 
 | ||||||
|         unsafe { |         unsafe { | ||||||
| @ -308,8 +308,7 @@ fn write_word<W: Word>(regs: &'static crate::pac::spi::Spi, word: W) -> Result<( | |||||||
|         } |         } | ||||||
|         if sr.txe() { |         if sr.txe() { | ||||||
|             unsafe { |             unsafe { | ||||||
|                 let dr = regs.dr().ptr() as *mut W; |                 ptr::write_volatile(regs.tx_ptr(), word); | ||||||
|                 ptr::write_volatile(dr, word); |  | ||||||
|             } |             } | ||||||
|             return Ok(()); |             return Ok(()); | ||||||
|         } |         } | ||||||
| @ -335,8 +334,7 @@ fn read_word<W: Word>(regs: &'static crate::pac::spi::Spi) -> Result<W, Error> { | |||||||
|         } |         } | ||||||
|         if sr.rxne() { |         if sr.rxne() { | ||||||
|             unsafe { |             unsafe { | ||||||
|                 let dr = regs.dr().ptr() as *const W; |                 return Ok(ptr::read_volatile(regs.rx_ptr())); | ||||||
|                 return Ok(ptr::read_volatile(dr)); |  | ||||||
|             } |             } | ||||||
|         } |         } | ||||||
|     } |     } | ||||||
|  | |||||||
| @ -2,7 +2,7 @@ | |||||||
| 
 | 
 | ||||||
| use crate::dma::NoDma; | use crate::dma::NoDma; | ||||||
| use crate::gpio::sealed::Pin; | use crate::gpio::sealed::Pin; | ||||||
| use crate::spi::{Error, Instance, RxDmaChannel, TxDmaChannel, WordSize}; | use crate::spi::{Error, Instance, RegsExt, RxDmaChannel, TxDmaChannel, WordSize}; | ||||||
| use core::future::Future; | use core::future::Future; | ||||||
| use core::ptr; | use core::ptr; | ||||||
| use embassy_traits::spi as traits; | use embassy_traits::spi as traits; | ||||||
| @ -44,7 +44,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { | |||||||
|         self.set_word_size(WordSize::EightBit); |         self.set_word_size(WordSize::EightBit); | ||||||
| 
 | 
 | ||||||
|         let request = self.txdma.request(); |         let request = self.txdma.request(); | ||||||
|         let dst = T::regs().dr().ptr() as *mut u8; |         let dst = T::regs().tx_ptr(); | ||||||
|         let f = self.txdma.write(request, write, dst); |         let f = self.txdma.write(request, write, dst); | ||||||
| 
 | 
 | ||||||
|         unsafe { |         unsafe { | ||||||
| @ -88,11 +88,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { | |||||||
|         let clock_byte_count = read.len(); |         let clock_byte_count = read.len(); | ||||||
| 
 | 
 | ||||||
|         let rx_request = self.rxdma.request(); |         let rx_request = self.rxdma.request(); | ||||||
|         let rx_src = T::regs().dr().ptr() as *mut u8; |         let rx_src = T::regs().rx_ptr(); | ||||||
|         let rx_f = self.rxdma.read(rx_request, rx_src, read); |         let rx_f = self.rxdma.read(rx_request, rx_src, read); | ||||||
| 
 | 
 | ||||||
|         let tx_request = self.txdma.request(); |         let tx_request = self.txdma.request(); | ||||||
|         let tx_dst = T::regs().dr().ptr() as *mut u8; |         let tx_dst = T::regs().tx_ptr(); | ||||||
|         let clock_byte = 0x00; |         let clock_byte = 0x00; | ||||||
|         let tx_f = self |         let tx_f = self | ||||||
|             .txdma |             .txdma | ||||||
| @ -146,13 +146,13 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { | |||||||
|         self.set_word_size(WordSize::EightBit); |         self.set_word_size(WordSize::EightBit); | ||||||
| 
 | 
 | ||||||
|         let rx_request = self.rxdma.request(); |         let rx_request = self.rxdma.request(); | ||||||
|         let rx_src = T::regs().dr().ptr() as *mut u8; |         let rx_src = T::regs().rx_ptr(); | ||||||
|         let rx_f = self |         let rx_f = self | ||||||
|             .rxdma |             .rxdma | ||||||
|             .read(rx_request, rx_src, &mut read[0..write.len()]); |             .read(rx_request, rx_src, &mut read[0..write.len()]); | ||||||
| 
 | 
 | ||||||
|         let tx_request = self.txdma.request(); |         let tx_request = self.txdma.request(); | ||||||
|         let tx_dst = T::regs().dr().ptr() as *mut u8; |         let tx_dst = T::regs().tx_ptr(); | ||||||
|         let tx_f = self.txdma.write(tx_request, write, tx_dst); |         let tx_f = self.txdma.write(tx_request, write, tx_dst); | ||||||
| 
 | 
 | ||||||
|         unsafe { |         unsafe { | ||||||
| @ -223,8 +223,7 @@ fn write_word<W: Word>(regs: &'static crate::pac::spi::Spi, word: W) -> Result<( | |||||||
|             return Err(Error::Crc); |             return Err(Error::Crc); | ||||||
|         } else if sr.txe() { |         } else if sr.txe() { | ||||||
|             unsafe { |             unsafe { | ||||||
|                 let dr = regs.dr().ptr() as *mut W; |                 ptr::write_volatile(regs.tx_ptr(), word); | ||||||
|                 ptr::write_volatile(dr, word); |  | ||||||
|             } |             } | ||||||
|             return Ok(()); |             return Ok(()); | ||||||
|         } |         } | ||||||
| @ -245,8 +244,7 @@ fn read_word<W: Word>(regs: &'static crate::pac::spi::Spi) -> Result<W, Error> { | |||||||
|             return Err(Error::Crc); |             return Err(Error::Crc); | ||||||
|         } else if sr.rxne() { |         } else if sr.rxne() { | ||||||
|             unsafe { |             unsafe { | ||||||
|                 let dr = regs.dr().ptr() as *const W; |                 return Ok(ptr::read_volatile(regs.rx_ptr())); | ||||||
|                 return Ok(ptr::read_volatile(dr)); |  | ||||||
|             } |             } | ||||||
|         } |         } | ||||||
|     } |     } | ||||||
|  | |||||||
| @ -2,7 +2,7 @@ | |||||||
| 
 | 
 | ||||||
| use crate::dma::NoDma; | use crate::dma::NoDma; | ||||||
| use crate::gpio::sealed::Pin; | use crate::gpio::sealed::Pin; | ||||||
| use crate::spi::{Error, Instance, RxDmaChannel, TxDmaChannel, WordSize}; | use crate::spi::{Error, Instance, RegsExt, RxDmaChannel, TxDmaChannel, WordSize}; | ||||||
| use core::future::Future; | use core::future::Future; | ||||||
| use core::ptr; | use core::ptr; | ||||||
| use embassy_traits::spi as traits; | use embassy_traits::spi as traits; | ||||||
| @ -49,7 +49,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { | |||||||
|         } |         } | ||||||
| 
 | 
 | ||||||
|         let request = self.txdma.request(); |         let request = self.txdma.request(); | ||||||
|         let dst = T::regs().txdr().ptr() as *mut u8; |         let dst = T::regs().tx_ptr(); | ||||||
|         let f = self.txdma.write(request, write, dst); |         let f = self.txdma.write(request, write, dst); | ||||||
| 
 | 
 | ||||||
|         unsafe { |         unsafe { | ||||||
| @ -96,11 +96,11 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { | |||||||
|         let clock_byte_count = read.len(); |         let clock_byte_count = read.len(); | ||||||
| 
 | 
 | ||||||
|         let rx_request = self.rxdma.request(); |         let rx_request = self.rxdma.request(); | ||||||
|         let rx_src = T::regs().rxdr().ptr() as *mut u8; |         let rx_src = T::regs().rx_ptr(); | ||||||
|         let rx_f = self.rxdma.read(rx_request, rx_src, read); |         let rx_f = self.rxdma.read(rx_request, rx_src, read); | ||||||
| 
 | 
 | ||||||
|         let tx_request = self.txdma.request(); |         let tx_request = self.txdma.request(); | ||||||
|         let tx_dst = T::regs().txdr().ptr() as *mut u8; |         let tx_dst = T::regs().tx_ptr(); | ||||||
|         let clock_byte = 0x00; |         let clock_byte = 0x00; | ||||||
|         let tx_f = self |         let tx_f = self | ||||||
|             .txdma |             .txdma | ||||||
| @ -155,13 +155,13 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> { | |||||||
|         } |         } | ||||||
| 
 | 
 | ||||||
|         let rx_request = self.rxdma.request(); |         let rx_request = self.rxdma.request(); | ||||||
|         let rx_src = T::regs().rxdr().ptr() as *mut u8; |         let rx_src = T::regs().rx_ptr(); | ||||||
|         let rx_f = self |         let rx_f = self | ||||||
|             .rxdma |             .rxdma | ||||||
|             .read(rx_request, rx_src, &mut read[0..write.len()]); |             .read(rx_request, rx_src, &mut read[0..write.len()]); | ||||||
| 
 | 
 | ||||||
|         let tx_request = self.txdma.request(); |         let tx_request = self.txdma.request(); | ||||||
|         let tx_dst = T::regs().txdr().ptr() as *mut u8; |         let tx_dst = T::regs().tx_ptr(); | ||||||
|         let tx_f = self.txdma.write(tx_request, write, tx_dst); |         let tx_f = self.txdma.write(tx_request, write, tx_dst); | ||||||
| 
 | 
 | ||||||
|         unsafe { |         unsafe { | ||||||
| @ -223,8 +223,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDm | |||||||
|                 // spin
 |                 // spin
 | ||||||
|             } |             } | ||||||
|             unsafe { |             unsafe { | ||||||
|                 let txdr = regs.txdr().ptr() as *mut u8; |                 ptr::write_volatile(regs.tx_ptr(), *word); | ||||||
|                 ptr::write_volatile(txdr, *word); |  | ||||||
|                 regs.cr1().modify(|reg| reg.set_cstart(true)); |                 regs.cr1().modify(|reg| reg.set_cstart(true)); | ||||||
|             } |             } | ||||||
|             loop { |             loop { | ||||||
| @ -245,9 +244,8 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDm | |||||||
|                 break; |                 break; | ||||||
|             } |             } | ||||||
|             unsafe { |             unsafe { | ||||||
|                 let rxdr = regs.rxdr().ptr() as *const u8; |  | ||||||
|                 // discard read to prevent pverrun.
 |                 // discard read to prevent pverrun.
 | ||||||
|                 let _ = ptr::read_volatile(rxdr); |                 let _: u8 = ptr::read_volatile(T::regs().rx_ptr()); | ||||||
|             } |             } | ||||||
|         } |         } | ||||||
| 
 | 
 | ||||||
| @ -276,8 +274,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, N | |||||||
|                 // spin
 |                 // spin
 | ||||||
|             } |             } | ||||||
|             unsafe { |             unsafe { | ||||||
|                 let txdr = regs.txdr().ptr() as *mut u8; |                 ptr::write_volatile(T::regs().tx_ptr(), *word); | ||||||
|                 ptr::write_volatile(txdr, *word); |  | ||||||
|                 regs.cr1().modify(|reg| reg.set_cstart(true)); |                 regs.cr1().modify(|reg| reg.set_cstart(true)); | ||||||
|             } |             } | ||||||
|             loop { |             loop { | ||||||
| @ -297,8 +294,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, N | |||||||
|                 } |                 } | ||||||
|             } |             } | ||||||
|             unsafe { |             unsafe { | ||||||
|                 let rxdr = regs.rxdr().ptr() as *const u8; |                 *word = ptr::read_volatile(T::regs().rx_ptr()); | ||||||
|                 *word = ptr::read_volatile(rxdr); |  | ||||||
|             } |             } | ||||||
|             let sr = unsafe { regs.sr().read() }; |             let sr = unsafe { regs.sr().read() }; | ||||||
|             if sr.tifre() { |             if sr.tifre() { | ||||||
|  | |||||||
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