nrf/spim: expose all functionality as inherent methods.
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				@ -133,9 +133,7 @@ impl<'d, T: Instance> Spim<'d, T> {
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        // Set over-read character
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					        // Set over-read character
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        let orc = config.orc;
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					        let orc = config.orc;
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        r.orc.write(|w|
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					        r.orc.write(|w| unsafe { w.orc().bits(orc) });
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            // The ORC field is 8 bits long, so any u8 is a valid value to write.
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            unsafe { w.orc().bits(orc) });
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        // Disable all events interrupts
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					        // Disable all events interrupts
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        r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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					        r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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@ -159,14 +157,11 @@ impl<'d, T: Instance> Spim<'d, T> {
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        }
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					        }
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    }
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					    }
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    fn start_transfer(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> {
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					    fn prepare(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> {
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        slice_in_ram_or(tx, Error::DMABufferNotInDataMemory)?;
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					        slice_in_ram_or(tx, Error::DMABufferNotInDataMemory)?;
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        // NOTE: RAM slice check for rx is not necessary, as a mutable
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					        // NOTE: RAM slice check for rx is not necessary, as a mutable
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        // slice can only be built from data located in RAM.
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					        // slice can only be built from data located in RAM.
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        // Conservative compiler fence to prevent optimizations that do not
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        // take in to account actions by DMA. The fence has been placed here,
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        // before any DMA action has started.
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        compiler_fence(Ordering::SeqCst);
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					        compiler_fence(Ordering::SeqCst);
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        let r = T::regs();
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					        let r = T::regs();
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@ -191,22 +186,19 @@ impl<'d, T: Instance> Spim<'d, T> {
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        Ok(())
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					        Ok(())
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    }
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					    }
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    fn blocking_transfer(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> {
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					    fn blocking_inner(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> {
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        self.start_transfer(rx, tx)?;
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					        self.prepare(rx, tx)?;
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        // Wait for 'end' event.
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					        // Wait for 'end' event.
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        while T::regs().events_end.read().bits() == 0 {}
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					        while T::regs().events_end.read().bits() == 0 {}
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        // Conservative compiler fence to prevent optimizations that do not
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        // take in to account actions by DMA. The fence has been placed here,
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        // after all possible DMA actions have completed.
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        compiler_fence(Ordering::SeqCst);
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					        compiler_fence(Ordering::SeqCst);
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        Ok(())
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					        Ok(())
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    }
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					    }
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    async fn async_transfer(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> {
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					    async fn async_inner(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> {
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        self.start_transfer(rx, tx)?;
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					        self.prepare(rx, tx)?;
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        // Wait for 'end' event.
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					        // Wait for 'end' event.
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        poll_fn(|cx| {
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					        poll_fn(|cx| {
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@ -219,13 +211,42 @@ impl<'d, T: Instance> Spim<'d, T> {
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        })
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					        })
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        .await;
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					        .await;
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        // Conservative compiler fence to prevent optimizations that do not
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        // take in to account actions by DMA. The fence has been placed here,
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        // after all possible DMA actions have completed.
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        compiler_fence(Ordering::SeqCst);
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					        compiler_fence(Ordering::SeqCst);
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        Ok(())
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					        Ok(())
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    }
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					    }
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					    pub fn blocking_read(&mut self, data: &mut [u8]) -> Result<(), Error> {
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					        self.blocking_inner(data, &[])
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					    }
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					    pub fn blocking_transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error> {
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					        self.blocking_inner(read, write)
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					    }
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					    pub fn blocking_transfer_in_place(&mut self, data: &mut [u8]) -> Result<(), Error> {
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					        self.blocking_inner(data, data)
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					    }
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					    pub fn blocking_write(&mut self, data: &[u8]) -> Result<(), Error> {
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					        self.blocking_inner(&mut [], data)
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					    }
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					    pub async fn read(&mut self, data: &mut [u8]) -> Result<(), Error> {
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					        self.async_inner(data, &[]).await
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					    }
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					    pub async fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error> {
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					        self.async_inner(read, write).await
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					    }
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					    pub async fn transfer_in_place(&mut self, data: &mut [u8]) -> Result<(), Error> {
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					        self.async_inner(data, data).await
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					    }
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					    pub async fn write(&mut self, data: &[u8]) -> Result<(), Error> {
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					        self.async_inner(&mut [], data).await
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					    }
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}
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					}
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impl<'d, T: Instance> Drop for Spim<'d, T> {
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					impl<'d, T: Instance> Drop for Spim<'d, T> {
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@ -257,7 +278,7 @@ impl<'d, T: Instance> Read<u8> for Spim<'d, T> {
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    = impl Future<Output = Result<(), Self::Error>> + 'a;
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					    = impl Future<Output = Result<(), Self::Error>> + 'a;
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    fn read<'a>(&'a mut self, data: &'a mut [u8]) -> Self::ReadFuture<'a> {
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					    fn read<'a>(&'a mut self, data: &'a mut [u8]) -> Self::ReadFuture<'a> {
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        self.read_write(data, &[])
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					        self.read(data)
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    }
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					    }
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}
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					}
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@ -268,7 +289,7 @@ impl<'d, T: Instance> Write<u8> for Spim<'d, T> {
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    = impl Future<Output = Result<(), Self::Error>> + 'a;
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					    = impl Future<Output = Result<(), Self::Error>> + 'a;
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    fn write<'a>(&'a mut self, data: &'a [u8]) -> Self::WriteFuture<'a> {
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					    fn write<'a>(&'a mut self, data: &'a [u8]) -> Self::WriteFuture<'a> {
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        self.read_write(&mut [], data)
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					        self.write(data)
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    }
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					    }
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}
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					}
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@ -279,14 +300,14 @@ impl<'d, T: Instance> FullDuplex<u8> for Spim<'d, T> {
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    = impl Future<Output = Result<(), Self::Error>> + 'a;
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					    = impl Future<Output = Result<(), Self::Error>> + 'a;
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    fn read_write<'a>(&'a mut self, rx: &'a mut [u8], tx: &'a [u8]) -> Self::WriteReadFuture<'a> {
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					    fn read_write<'a>(&'a mut self, rx: &'a mut [u8], tx: &'a [u8]) -> Self::WriteReadFuture<'a> {
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        self.async_transfer(rx, tx)
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					        self.transfer(rx, tx)
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    }
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					    }
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}
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					}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spim<'d, T> {
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					impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spim<'d, T> {
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    type Error = Error;
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					    type Error = Error;
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    fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
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					    fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
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        self.blocking_transfer(words, words)?;
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					        self.blocking_transfer_in_place(words)?;
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        Ok(words)
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					        Ok(words)
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    }
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					    }
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}
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					}
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@ -295,7 +316,7 @@ impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spim<'d, T> {
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    type Error = Error;
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					    type Error = Error;
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    fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
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					    fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
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        self.blocking_transfer(&mut [], words)
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					        self.blocking_write(words)
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    }
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					    }
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}
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					}
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@ -9,7 +9,6 @@ use embassy::executor::Spawner;
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use embassy_nrf::gpio::{Level, Output, OutputDrive};
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					use embassy_nrf::gpio::{Level, Output, OutputDrive};
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use embassy_nrf::Peripherals;
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					use embassy_nrf::Peripherals;
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use embassy_nrf::{interrupt, spim};
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					use embassy_nrf::{interrupt, spim};
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use embassy_traits::spi::FullDuplex;
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use example_common::*;
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					use example_common::*;
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#[embassy::main]
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					#[embassy::main]
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@ -31,7 +30,7 @@ async fn main(_spawner: Spawner, p: Peripherals) {
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    ncs.set_low();
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					    ncs.set_low();
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    cortex_m::asm::delay(5);
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					    cortex_m::asm::delay(5);
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    let tx = [0xFF];
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					    let tx = [0xFF];
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    unwrap!(spim.read_write(&mut [], &tx).await);
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					    unwrap!(spim.transfer(&mut [], &tx).await);
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    cortex_m::asm::delay(10);
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					    cortex_m::asm::delay(10);
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    ncs.set_high();
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					    ncs.set_high();
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@ -44,7 +43,7 @@ async fn main(_spawner: Spawner, p: Peripherals) {
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    ncs.set_low();
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					    ncs.set_low();
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    cortex_m::asm::delay(5000);
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					    cortex_m::asm::delay(5000);
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    let tx = [0b000_11101, 0];
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					    let tx = [0b000_11101, 0];
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    unwrap!(spim.read_write(&mut rx, &tx).await);
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					    unwrap!(spim.transfer(&mut rx, &tx).await);
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    cortex_m::asm::delay(5000);
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					    cortex_m::asm::delay(5000);
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    ncs.set_high();
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					    ncs.set_high();
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    info!("estat: {=[?]}", rx);
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					    info!("estat: {=[?]}", rx);
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@ -54,7 +53,7 @@ async fn main(_spawner: Spawner, p: Peripherals) {
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    ncs.set_low();
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					    ncs.set_low();
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    cortex_m::asm::delay(5);
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					    cortex_m::asm::delay(5);
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    let tx = [0b100_11111, 0b11];
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					    let tx = [0b100_11111, 0b11];
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    unwrap!(spim.read_write(&mut rx, &tx).await);
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					    unwrap!(spim.transfer(&mut rx, &tx).await);
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    cortex_m::asm::delay(10);
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					    cortex_m::asm::delay(10);
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    ncs.set_high();
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					    ncs.set_high();
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@ -63,7 +62,7 @@ async fn main(_spawner: Spawner, p: Peripherals) {
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    ncs.set_low();
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					    ncs.set_low();
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    cortex_m::asm::delay(5);
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					    cortex_m::asm::delay(5);
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    let tx = [0b000_10010, 0];
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					    let tx = [0b000_10010, 0];
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    unwrap!(spim.read_write(&mut rx, &tx).await);
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					    unwrap!(spim.transfer(&mut rx, &tx).await);
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    cortex_m::asm::delay(10);
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					    cortex_m::asm::delay(10);
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    ncs.set_high();
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					    ncs.set_high();
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