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Replace wait_for_idle with spin_until_idle

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This commit is contained in:
Grant Miller 2021-12-14 16:05:39 -06:00
parent e75cb1a564
commit a13a7a6616
4 changed files with 46 additions and 43 deletions
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20
embassy-stm32/src/spi/mod.rs
View File

@ -431,6 +431,26 @@ fn spin_until_rx_ready(regs: Regs) -> Result<(), Error> {
} }
} }
fn spin_until_idle(regs: Regs) {
#[cfg(any(spi_v1, spi_f1))]
unsafe {
while regs.sr().read().bsy() {}
}
#[cfg(spi_v2)]
unsafe {
while regs.sr().read().ftlvl() > 0 {}
while regs.sr().read().frlvl() > 0 {}
while regs.sr().read().bsy() {}
}
#[cfg(spi_v3)]
unsafe {
while !regs.sr().read().txc() {}
while regs.sr().read().rxplvl().0 > 0 {}
}
}
trait Word { trait Word {
const WORDSIZE: WordSize; const WORDSIZE: WordSize;
} }

18
embassy-stm32/src/spi/v1.rs
View File

@ -2,7 +2,7 @@
pub use embedded_hal::blocking; pub use embedded_hal::blocking;
pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
use futures::future::join3; use futures::future::join;
use super::*; use super::*;
@ -76,7 +76,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}); });
} }
join3(tx_f, rx_f, Self::wait_for_idle()).await; join(tx_f, rx_f).await;
spin_until_idle(T::regs());
unsafe { unsafe {
T::regs().cr2().modify(|reg| { T::regs().cr2().modify(|reg| {
@ -134,7 +136,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}); });
} }
join3(tx_f, rx_f, Self::wait_for_idle()).await; join(tx_f, rx_f).await;
spin_until_idle(T::regs());
unsafe { unsafe {
T::regs().cr2().modify(|reg| { T::regs().cr2().modify(|reg| {
@ -148,12 +152,4 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
Ok(()) Ok(())
} }
async fn wait_for_idle() {
unsafe {
while T::regs().sr().read().bsy() {
// spin
}
}
}
} }

28
embassy-stm32/src/spi/v2.rs
View File

@ -1,7 +1,7 @@
#![macro_use] #![macro_use]
pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
use futures::future::{join, join3}; use futures::future::join;
use super::*; use super::*;
@ -35,7 +35,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}); });
} }
join(f, Self::wait_for_idle()).await; f.await;
spin_until_idle(T::regs());
unsafe { unsafe {
T::regs().cr2().modify(|reg| { T::regs().cr2().modify(|reg| {
@ -89,7 +91,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}); });
} }
join3(tx_f, rx_f, Self::wait_for_idle()).await; join(tx_f, rx_f).await;
spin_until_idle(T::regs());
unsafe { unsafe {
T::regs().cr2().modify(|reg| { T::regs().cr2().modify(|reg| {
@ -152,7 +156,9 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}); });
} }
join3(tx_f, rx_f, Self::wait_for_idle()).await; join(tx_f, rx_f).await;
spin_until_idle(T::regs());
unsafe { unsafe {
T::regs().cr2().modify(|reg| { T::regs().cr2().modify(|reg| {
@ -166,18 +172,4 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
Ok(()) Ok(())
} }
async fn wait_for_idle() {
unsafe {
while T::regs().sr().read().ftlvl() > 0 {
// spin
}
while T::regs().sr().read().frlvl() > 0 {
// spin
}
while T::regs().sr().read().bsy() {
// spin
}
}
}
} }

23
embassy-stm32/src/spi/v3.rs
View File

@ -1,7 +1,7 @@
#![macro_use] #![macro_use]
pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3}; pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
use futures::future::join3; use futures::future::join;
use super::*; use super::*;
@ -95,7 +95,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}); });
} }
join3(tx_f, rx_f, Self::wait_for_idle()).await; join(tx_f, rx_f).await;
spin_until_idle(T::regs());
unsafe { unsafe {
T::regs().cfg1().modify(|reg| { T::regs().cfg1().modify(|reg| {
reg.set_rxdmaen(false); reg.set_rxdmaen(false);
@ -159,7 +162,10 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}); });
} }
join3(tx_f, rx_f, Self::wait_for_idle()).await; join(tx_f, rx_f).await;
spin_until_idle(T::regs());
unsafe { unsafe {
T::regs().cfg1().modify(|reg| { T::regs().cfg1().modify(|reg| {
reg.set_rxdmaen(false); reg.set_rxdmaen(false);
@ -171,15 +177,4 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
} }
Ok(()) Ok(())
} }
async fn wait_for_idle() {
unsafe {
while !T::regs().sr().read().txc() {
// spin
}
while T::regs().sr().read().rxplvl().0 > 0 {
// spin
}
}
}
} }