diff --git a/embassy-rp/src/lib.rs b/embassy-rp/src/lib.rs
index 8b0023ea5..80ee47802 100644
--- a/embassy-rp/src/lib.rs
+++ b/embassy-rp/src/lib.rs
@@ -656,9 +656,27 @@ unsafe fn pre_init() {
         // We can still use PSM to reset PROC1 since it comes after PROC0 in the state machine.
         pac::PSM.frce_off().write_and_wait(|w| w.set_proc1(true));
         pac::PSM.frce_off().write_and_wait(|_| {});
+
+        // Make atomics work between cores.
+        enable_actlr_extexclall();
     }
 }
 
+/// Set the EXTEXCLALL bit in ACTLR.
+///
+/// The default MPU memory map marks all memory as non-shareable, so atomics don't
+/// synchronize memory accesses between cores at all. This bit forces all memory to be
+/// considered shareable regardless of what the MPU says.
+///
+/// TODO: does this interfere somehow if the user wants to use a custom MPU configuration?
+/// maybe we need to add a way to disable this?
+///
+/// This must be done FOR EACH CORE.
+#[cfg(feature = "_rp235x")]
+unsafe fn enable_actlr_extexclall() {
+    (&*cortex_m::peripheral::ICB::PTR).actlr.modify(|w| w | (1 << 29));
+}
+
 /// Extension trait for PAC regs, adding atomic xor/bitset/bitclear writes.
 #[allow(unused)]
 trait RegExt<T: Copy> {
diff --git a/embassy-rp/src/multicore.rs b/embassy-rp/src/multicore.rs
index ea0a29a36..1450505b9 100644
--- a/embassy-rp/src/multicore.rs
+++ b/embassy-rp/src/multicore.rs
@@ -65,6 +65,10 @@ unsafe fn core1_setup(stack_bottom: *mut usize) {
         // embassy, somehow. trap if so since we can't deal with that.
         cortex_m::asm::udf();
     }
+
+    #[cfg(feature = "_rp235x")]
+    crate::enable_actlr_extexclall();
+
     unsafe {
         gpio::init();
     }