Merge pull request #3731 from embassy-rs/update-metapac-yet-again
Update stm32-metapac.
This commit is contained in:
Dario Nieuwenhuis
GitHub
commit
8a9ca88cc4
@ -73,7 +73,7 @@ rand_core = "0.6.3"
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sdio-host = "0.5.0"
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critical-section = "1.1"
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#stm32-metapac = { version = "15" }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-274eeb0ed4477768d026276c4e9873586c1b9a05" }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-fad4bc0f2baac29ecebb5153d2997b649b71025f" }
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vcell = "0.1.3"
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nb = "1.0.0"
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@ -102,7 +102,7 @@ proc-macro2 = "1.0.36"
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quote = "1.0.15"
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#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-274eeb0ed4477768d026276c4e9873586c1b9a05", default-features = false, features = ["metadata"] }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-fad4bc0f2baac29ecebb5153d2997b649b71025f", default-features = false, features = ["metadata"] }
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[features]
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default = ["rt"]
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@ -127,8 +127,8 @@ exti = []
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low-power = [ "dep:embassy-executor", "embassy-executor?/arch-cortex-m", "time" ]
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low-power-debug-with-sleep = []
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## Automatically generate `memory.x` file using [`stm32-metapac`](https://docs.rs/stm32-metapac/)
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memory-x = ["stm32-metapac/memory-x"]
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## Automatically generate `memory.x` file based on the memory map from [`stm32-metapac`](https://docs.rs/stm32-metapac/)
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memory-x = []
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## Use secure registers when TrustZone is enabled
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trustzone-secure = []
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@ -202,6 +202,9 @@ _split-pins-enabled = []
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## internal use only
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_dual-core = []
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_core-cm0p = []
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_core-cm4 = []
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_core-cm7 = []
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#! ## Chip-selection features
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#! Select your chip by specifying the model as a feature, e.g. `stm32c011d6`.
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@ -1026,40 +1029,40 @@ stm32h743xg = [ "stm32-metapac/stm32h743xg" ]
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stm32h743xi = [ "stm32-metapac/stm32h743xi" ]
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stm32h743zg = [ "stm32-metapac/stm32h743zg" ]
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stm32h743zi = [ "stm32-metapac/stm32h743zi" ]
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stm32h745bg-cm7 = [ "stm32-metapac/stm32h745bg-cm7", "_dual-core" ]
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stm32h745bg-cm4 = [ "stm32-metapac/stm32h745bg-cm4", "_dual-core" ]
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stm32h745bi-cm7 = [ "stm32-metapac/stm32h745bi-cm7", "_dual-core" ]
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stm32h745bi-cm4 = [ "stm32-metapac/stm32h745bi-cm4", "_dual-core" ]
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stm32h745ig-cm7 = [ "stm32-metapac/stm32h745ig-cm7", "_dual-core" ]
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stm32h745ig-cm4 = [ "stm32-metapac/stm32h745ig-cm4", "_dual-core" ]
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stm32h745ii-cm7 = [ "stm32-metapac/stm32h745ii-cm7", "_dual-core" ]
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stm32h745ii-cm4 = [ "stm32-metapac/stm32h745ii-cm4", "_dual-core" ]
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stm32h745xg-cm7 = [ "stm32-metapac/stm32h745xg-cm7", "_dual-core" ]
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stm32h745xg-cm4 = [ "stm32-metapac/stm32h745xg-cm4", "_dual-core" ]
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stm32h745xi-cm7 = [ "stm32-metapac/stm32h745xi-cm7", "_dual-core" ]
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stm32h745xi-cm4 = [ "stm32-metapac/stm32h745xi-cm4", "_dual-core" ]
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stm32h745zg-cm7 = [ "stm32-metapac/stm32h745zg-cm7", "_dual-core" ]
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stm32h745zg-cm4 = [ "stm32-metapac/stm32h745zg-cm4", "_dual-core" ]
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stm32h745zi-cm7 = [ "stm32-metapac/stm32h745zi-cm7", "_dual-core" ]
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stm32h745zi-cm4 = [ "stm32-metapac/stm32h745zi-cm4", "_dual-core" ]
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stm32h747ag-cm7 = [ "stm32-metapac/stm32h747ag-cm7", "_dual-core" ]
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stm32h747ag-cm4 = [ "stm32-metapac/stm32h747ag-cm4", "_dual-core" ]
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stm32h747ai-cm7 = [ "stm32-metapac/stm32h747ai-cm7", "_dual-core" ]
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stm32h747ai-cm4 = [ "stm32-metapac/stm32h747ai-cm4", "_dual-core" ]
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stm32h747bg-cm7 = [ "stm32-metapac/stm32h747bg-cm7", "_dual-core" ]
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stm32h747bg-cm4 = [ "stm32-metapac/stm32h747bg-cm4", "_dual-core" ]
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stm32h747bi-cm7 = [ "stm32-metapac/stm32h747bi-cm7", "_dual-core" ]
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stm32h747bi-cm4 = [ "stm32-metapac/stm32h747bi-cm4", "_dual-core" ]
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stm32h747ig-cm7 = [ "stm32-metapac/stm32h747ig-cm7", "_dual-core" ]
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stm32h747ig-cm4 = [ "stm32-metapac/stm32h747ig-cm4", "_dual-core" ]
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stm32h747ii-cm7 = [ "stm32-metapac/stm32h747ii-cm7", "_dual-core" ]
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stm32h747ii-cm4 = [ "stm32-metapac/stm32h747ii-cm4", "_dual-core" ]
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stm32h747xg-cm7 = [ "stm32-metapac/stm32h747xg-cm7", "_dual-core" ]
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stm32h747xg-cm4 = [ "stm32-metapac/stm32h747xg-cm4", "_dual-core" ]
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stm32h747xi-cm7 = [ "stm32-metapac/stm32h747xi-cm7", "_dual-core" ]
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stm32h747xi-cm4 = [ "stm32-metapac/stm32h747xi-cm4", "_dual-core" ]
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stm32h747zi-cm7 = [ "stm32-metapac/stm32h747zi-cm7", "_dual-core" ]
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stm32h747zi-cm4 = [ "stm32-metapac/stm32h747zi-cm4", "_dual-core" ]
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stm32h745bg-cm7 = [ "stm32-metapac/stm32h745bg-cm7", "_dual-core", "_core-cm7" ]
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stm32h745bg-cm4 = [ "stm32-metapac/stm32h745bg-cm4", "_dual-core", "_core-cm4" ]
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stm32h745bi-cm7 = [ "stm32-metapac/stm32h745bi-cm7", "_dual-core", "_core-cm7" ]
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stm32h745bi-cm4 = [ "stm32-metapac/stm32h745bi-cm4", "_dual-core", "_core-cm4" ]
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stm32h745ig-cm7 = [ "stm32-metapac/stm32h745ig-cm7", "_dual-core", "_core-cm7" ]
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stm32h745ig-cm4 = [ "stm32-metapac/stm32h745ig-cm4", "_dual-core", "_core-cm4" ]
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stm32h745ii-cm7 = [ "stm32-metapac/stm32h745ii-cm7", "_dual-core", "_core-cm7" ]
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stm32h745ii-cm4 = [ "stm32-metapac/stm32h745ii-cm4", "_dual-core", "_core-cm4" ]
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stm32h745xg-cm7 = [ "stm32-metapac/stm32h745xg-cm7", "_dual-core", "_core-cm7" ]
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stm32h745xg-cm4 = [ "stm32-metapac/stm32h745xg-cm4", "_dual-core", "_core-cm4" ]
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stm32h745xi-cm7 = [ "stm32-metapac/stm32h745xi-cm7", "_dual-core", "_core-cm7" ]
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stm32h745xi-cm4 = [ "stm32-metapac/stm32h745xi-cm4", "_dual-core", "_core-cm4" ]
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stm32h745zg-cm7 = [ "stm32-metapac/stm32h745zg-cm7", "_dual-core", "_core-cm7" ]
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stm32h745zg-cm4 = [ "stm32-metapac/stm32h745zg-cm4", "_dual-core", "_core-cm4" ]
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stm32h745zi-cm7 = [ "stm32-metapac/stm32h745zi-cm7", "_dual-core", "_core-cm7" ]
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stm32h745zi-cm4 = [ "stm32-metapac/stm32h745zi-cm4", "_dual-core", "_core-cm4" ]
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stm32h747ag-cm7 = [ "stm32-metapac/stm32h747ag-cm7", "_dual-core", "_core-cm7" ]
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stm32h747ag-cm4 = [ "stm32-metapac/stm32h747ag-cm4", "_dual-core", "_core-cm4" ]
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stm32h747ai-cm7 = [ "stm32-metapac/stm32h747ai-cm7", "_dual-core", "_core-cm7" ]
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stm32h747ai-cm4 = [ "stm32-metapac/stm32h747ai-cm4", "_dual-core", "_core-cm4" ]
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stm32h747bg-cm7 = [ "stm32-metapac/stm32h747bg-cm7", "_dual-core", "_core-cm7" ]
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stm32h747bg-cm4 = [ "stm32-metapac/stm32h747bg-cm4", "_dual-core", "_core-cm4" ]
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stm32h747bi-cm7 = [ "stm32-metapac/stm32h747bi-cm7", "_dual-core", "_core-cm7" ]
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stm32h747bi-cm4 = [ "stm32-metapac/stm32h747bi-cm4", "_dual-core", "_core-cm4" ]
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stm32h747ig-cm7 = [ "stm32-metapac/stm32h747ig-cm7", "_dual-core", "_core-cm7" ]
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stm32h747ig-cm4 = [ "stm32-metapac/stm32h747ig-cm4", "_dual-core", "_core-cm4" ]
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stm32h747ii-cm7 = [ "stm32-metapac/stm32h747ii-cm7", "_dual-core", "_core-cm7" ]
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stm32h747ii-cm4 = [ "stm32-metapac/stm32h747ii-cm4", "_dual-core", "_core-cm4" ]
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stm32h747xg-cm7 = [ "stm32-metapac/stm32h747xg-cm7", "_dual-core", "_core-cm7" ]
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stm32h747xg-cm4 = [ "stm32-metapac/stm32h747xg-cm4", "_dual-core", "_core-cm4" ]
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stm32h747xi-cm7 = [ "stm32-metapac/stm32h747xi-cm7", "_dual-core", "_core-cm7" ]
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stm32h747xi-cm4 = [ "stm32-metapac/stm32h747xi-cm4", "_dual-core", "_core-cm4" ]
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stm32h747zi-cm7 = [ "stm32-metapac/stm32h747zi-cm7", "_dual-core", "_core-cm7" ]
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stm32h747zi-cm4 = [ "stm32-metapac/stm32h747zi-cm4", "_dual-core", "_core-cm4" ]
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stm32h750ib = [ "stm32-metapac/stm32h750ib" ]
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stm32h750vb = [ "stm32-metapac/stm32h750vb" ]
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stm32h750xb = [ "stm32-metapac/stm32h750xb" ]
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@ -1070,24 +1073,24 @@ stm32h753ii = [ "stm32-metapac/stm32h753ii" ]
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stm32h753vi = [ "stm32-metapac/stm32h753vi" ]
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stm32h753xi = [ "stm32-metapac/stm32h753xi" ]
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stm32h753zi = [ "stm32-metapac/stm32h753zi" ]
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stm32h755bi-cm7 = [ "stm32-metapac/stm32h755bi-cm7", "_dual-core" ]
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stm32h755bi-cm4 = [ "stm32-metapac/stm32h755bi-cm4", "_dual-core" ]
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stm32h755ii-cm7 = [ "stm32-metapac/stm32h755ii-cm7", "_dual-core" ]
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stm32h755ii-cm4 = [ "stm32-metapac/stm32h755ii-cm4", "_dual-core" ]
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stm32h755xi-cm7 = [ "stm32-metapac/stm32h755xi-cm7", "_dual-core" ]
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stm32h755xi-cm4 = [ "stm32-metapac/stm32h755xi-cm4", "_dual-core" ]
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stm32h755zi-cm7 = [ "stm32-metapac/stm32h755zi-cm7", "_dual-core" ]
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stm32h755zi-cm4 = [ "stm32-metapac/stm32h755zi-cm4", "_dual-core" ]
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stm32h757ai-cm7 = [ "stm32-metapac/stm32h757ai-cm7", "_dual-core" ]
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stm32h757ai-cm4 = [ "stm32-metapac/stm32h757ai-cm4", "_dual-core" ]
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stm32h757bi-cm7 = [ "stm32-metapac/stm32h757bi-cm7", "_dual-core" ]
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stm32h757bi-cm4 = [ "stm32-metapac/stm32h757bi-cm4", "_dual-core" ]
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stm32h757ii-cm7 = [ "stm32-metapac/stm32h757ii-cm7", "_dual-core" ]
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stm32h757ii-cm4 = [ "stm32-metapac/stm32h757ii-cm4", "_dual-core" ]
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stm32h757xi-cm7 = [ "stm32-metapac/stm32h757xi-cm7", "_dual-core" ]
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stm32h757xi-cm4 = [ "stm32-metapac/stm32h757xi-cm4", "_dual-core" ]
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stm32h757zi-cm7 = [ "stm32-metapac/stm32h757zi-cm7", "_dual-core" ]
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stm32h757zi-cm4 = [ "stm32-metapac/stm32h757zi-cm4", "_dual-core" ]
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stm32h755bi-cm7 = [ "stm32-metapac/stm32h755bi-cm7", "_dual-core", "_core-cm7" ]
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stm32h755bi-cm4 = [ "stm32-metapac/stm32h755bi-cm4", "_dual-core", "_core-cm4" ]
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stm32h755ii-cm7 = [ "stm32-metapac/stm32h755ii-cm7", "_dual-core", "_core-cm7" ]
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stm32h755ii-cm4 = [ "stm32-metapac/stm32h755ii-cm4", "_dual-core", "_core-cm4" ]
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stm32h755xi-cm7 = [ "stm32-metapac/stm32h755xi-cm7", "_dual-core", "_core-cm7" ]
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stm32h755xi-cm4 = [ "stm32-metapac/stm32h755xi-cm4", "_dual-core", "_core-cm4" ]
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stm32h755zi-cm7 = [ "stm32-metapac/stm32h755zi-cm7", "_dual-core", "_core-cm7" ]
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stm32h755zi-cm4 = [ "stm32-metapac/stm32h755zi-cm4", "_dual-core", "_core-cm4" ]
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stm32h757ai-cm7 = [ "stm32-metapac/stm32h757ai-cm7", "_dual-core", "_core-cm7" ]
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stm32h757ai-cm4 = [ "stm32-metapac/stm32h757ai-cm4", "_dual-core", "_core-cm4" ]
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stm32h757bi-cm7 = [ "stm32-metapac/stm32h757bi-cm7", "_dual-core", "_core-cm7" ]
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stm32h757bi-cm4 = [ "stm32-metapac/stm32h757bi-cm4", "_dual-core", "_core-cm4" ]
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stm32h757ii-cm7 = [ "stm32-metapac/stm32h757ii-cm7", "_dual-core", "_core-cm7" ]
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stm32h757ii-cm4 = [ "stm32-metapac/stm32h757ii-cm4", "_dual-core", "_core-cm4" ]
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stm32h757xi-cm7 = [ "stm32-metapac/stm32h757xi-cm7", "_dual-core", "_core-cm7" ]
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stm32h757xi-cm4 = [ "stm32-metapac/stm32h757xi-cm4", "_dual-core", "_core-cm4" ]
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stm32h757zi-cm7 = [ "stm32-metapac/stm32h757zi-cm7", "_dual-core", "_core-cm7" ]
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stm32h757zi-cm4 = [ "stm32-metapac/stm32h757zi-cm4", "_dual-core", "_core-cm4" ]
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stm32h7a3ag = [ "stm32-metapac/stm32h7a3ag" ]
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stm32h7a3ai = [ "stm32-metapac/stm32h7a3ai" ]
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stm32h7a3ig = [ "stm32-metapac/stm32h7a3ig" ]
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@ -1620,14 +1623,14 @@ stm32wba55he = [ "stm32-metapac/stm32wba55he" ]
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stm32wba55hg = [ "stm32-metapac/stm32wba55hg" ]
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stm32wba55ue = [ "stm32-metapac/stm32wba55ue" ]
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stm32wba55ug = [ "stm32-metapac/stm32wba55ug" ]
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stm32wl54cc-cm4 = [ "stm32-metapac/stm32wl54cc-cm4", "_dual-core" ]
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stm32wl54cc-cm0p = [ "stm32-metapac/stm32wl54cc-cm0p", "_dual-core" ]
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stm32wl54jc-cm4 = [ "stm32-metapac/stm32wl54jc-cm4", "_dual-core" ]
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stm32wl54jc-cm0p = [ "stm32-metapac/stm32wl54jc-cm0p", "_dual-core" ]
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stm32wl55cc-cm4 = [ "stm32-metapac/stm32wl55cc-cm4", "_dual-core" ]
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stm32wl55cc-cm0p = [ "stm32-metapac/stm32wl55cc-cm0p", "_dual-core" ]
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stm32wl55jc-cm4 = [ "stm32-metapac/stm32wl55jc-cm4", "_dual-core" ]
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stm32wl55jc-cm0p = [ "stm32-metapac/stm32wl55jc-cm0p", "_dual-core" ]
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stm32wl54cc-cm4 = [ "stm32-metapac/stm32wl54cc-cm4", "_dual-core", "_core-cm4" ]
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stm32wl54cc-cm0p = [ "stm32-metapac/stm32wl54cc-cm0p", "_dual-core", "_core-cm0p" ]
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stm32wl54jc-cm4 = [ "stm32-metapac/stm32wl54jc-cm4", "_dual-core", "_core-cm4" ]
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stm32wl54jc-cm0p = [ "stm32-metapac/stm32wl54jc-cm0p", "_dual-core", "_core-cm0p" ]
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stm32wl55cc-cm4 = [ "stm32-metapac/stm32wl55cc-cm4", "_dual-core", "_core-cm4" ]
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stm32wl55cc-cm0p = [ "stm32-metapac/stm32wl55cc-cm0p", "_dual-core", "_core-cm0p" ]
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stm32wl55jc-cm4 = [ "stm32-metapac/stm32wl55jc-cm4", "_dual-core", "_core-cm4" ]
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stm32wl55jc-cm0p = [ "stm32-metapac/stm32wl55jc-cm0p", "_dual-core", "_core-cm0p" ]
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stm32wle4c8 = [ "stm32-metapac/stm32wle4c8" ]
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stm32wle4cb = [ "stm32-metapac/stm32wle4cb" ]
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stm32wle4cc = [ "stm32-metapac/stm32wle4cc" ]
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@ -9,8 +9,8 @@ use proc_macro2::{Ident, TokenStream};
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use quote::{format_ident, quote};
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use stm32_metapac::metadata::ir::BitOffset;
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use stm32_metapac::metadata::{
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MemoryRegionKind, PeripheralRccKernelClock, PeripheralRccRegister, PeripheralRegisters, StopMode, ALL_CHIPS,
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ALL_PERIPHERAL_VERSIONS, METADATA,
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MemoryRegion, MemoryRegionKind, PeripheralRccKernelClock, PeripheralRccRegister, PeripheralRegisters, StopMode,
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ALL_CHIPS, ALL_PERIPHERAL_VERSIONS, METADATA,
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};
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#[path = "./build_common.rs"]
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@ -1678,6 +1678,59 @@ fn main() {
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pub(crate) const DMA_CHANNELS: &[crate::dma::ChannelInfo] = &[#dmas];
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});
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// ========
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// Generate gpio_block() function
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let gpio_base = METADATA.peripherals.iter().find(|p| p.name == "GPIOA").unwrap().address as usize;
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let gpio_stride = 0x400 as usize;
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||||
|
||||
for p in METADATA.peripherals {
|
||||
if let Some(bi) = &p.registers {
|
||||
if bi.kind == "gpio" {
|
||||
assert_eq!(0, (p.address as usize - gpio_base) % gpio_stride);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
g.extend(quote!(
|
||||
pub fn gpio_block(n: usize) -> crate::pac::gpio::Gpio {{
|
||||
unsafe {{ crate::pac::gpio::Gpio::from_ptr((#gpio_base + #gpio_stride*n) as _) }}
|
||||
}}
|
||||
));
|
||||
|
||||
// ========
|
||||
// Generate flash constants
|
||||
|
||||
let flash_regions: Vec<&MemoryRegion> = METADATA
|
||||
.memory
|
||||
.iter()
|
||||
.filter(|x| x.kind == MemoryRegionKind::Flash && x.name.starts_with("BANK_"))
|
||||
.collect();
|
||||
let first_flash = flash_regions.first().unwrap();
|
||||
let total_flash_size = flash_regions
|
||||
.iter()
|
||||
.map(|x| x.size)
|
||||
.reduce(|acc, item| acc + item)
|
||||
.unwrap();
|
||||
let write_sizes: HashSet<_> = flash_regions
|
||||
.iter()
|
||||
.map(|r| r.settings.as_ref().unwrap().write_size)
|
||||
.collect();
|
||||
assert_eq!(1, write_sizes.len());
|
||||
|
||||
let flash_base = first_flash.address as usize;
|
||||
let total_flash_size = total_flash_size as usize;
|
||||
let write_size = (*write_sizes.iter().next().unwrap()) as usize;
|
||||
|
||||
g.extend(quote!(
|
||||
pub const FLASH_BASE: usize = #flash_base;
|
||||
pub const FLASH_SIZE: usize = #total_flash_size;
|
||||
pub const WRITE_SIZE: usize = #write_size;
|
||||
));
|
||||
|
||||
// ========
|
||||
// Generate macro-tables
|
||||
|
||||
for irq in METADATA.interrupts {
|
||||
let name = irq.name.to_ascii_uppercase();
|
||||
interrupts_table.push(vec![name.clone()]);
|
||||
@ -1772,6 +1825,11 @@ fn main() {
|
||||
}
|
||||
|
||||
println!("cargo:rerun-if-changed=build.rs");
|
||||
|
||||
if cfg!(feature = "memory-x") {
|
||||
gen_memory_x(out_dir);
|
||||
println!("cargo:rustc-link-search={}", out_dir.display());
|
||||
}
|
||||
}
|
||||
|
||||
enum GetOneError {
|
||||
@ -1857,3 +1915,78 @@ fn rustfmt(path: impl AsRef<Path>) {
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn gen_memory_x(out_dir: &Path) {
|
||||
let mut memory_x = String::new();
|
||||
|
||||
let flash = get_memory_range(MemoryRegionKind::Flash);
|
||||
let ram = get_memory_range(MemoryRegionKind::Ram);
|
||||
|
||||
write!(memory_x, "MEMORY\n{{\n").unwrap();
|
||||
writeln!(
|
||||
memory_x,
|
||||
" FLASH : ORIGIN = 0x{:08x}, LENGTH = {:>4}K /* {} */",
|
||||
flash.0,
|
||||
flash.1 / 1024,
|
||||
flash.2
|
||||
)
|
||||
.unwrap();
|
||||
writeln!(
|
||||
memory_x,
|
||||
" RAM : ORIGIN = 0x{:08x}, LENGTH = {:>4}K /* {} */",
|
||||
ram.0,
|
||||
ram.1 / 1024,
|
||||
ram.2
|
||||
)
|
||||
.unwrap();
|
||||
write!(memory_x, "}}").unwrap();
|
||||
|
||||
std::fs::write(out_dir.join("memory.x"), memory_x.as_bytes()).unwrap();
|
||||
}
|
||||
|
||||
fn get_memory_range(kind: MemoryRegionKind) -> (u32, u32, String) {
|
||||
let mut mems: Vec<_> = METADATA
|
||||
.memory
|
||||
.iter()
|
||||
.filter(|m| m.kind == kind && m.size != 0)
|
||||
.collect();
|
||||
mems.sort_by_key(|m| m.address);
|
||||
|
||||
let mut start = u32::MAX;
|
||||
let mut end = u32::MAX;
|
||||
let mut names = Vec::new();
|
||||
let mut best: Option<(u32, u32, String)> = None;
|
||||
for m in mems {
|
||||
if !mem_filter(&METADATA.name, &m.name) {
|
||||
continue;
|
||||
}
|
||||
|
||||
if m.address != end {
|
||||
names = Vec::new();
|
||||
start = m.address;
|
||||
end = m.address;
|
||||
}
|
||||
|
||||
end += m.size;
|
||||
names.push(m.name.to_string());
|
||||
|
||||
if best.is_none() || end - start > best.as_ref().unwrap().1 {
|
||||
best = Some((start, end - start, names.join(" + ")));
|
||||
}
|
||||
}
|
||||
|
||||
best.unwrap()
|
||||
}
|
||||
|
||||
fn mem_filter(chip: &str, region: &str) -> bool {
|
||||
// in STM32WB, SRAM2a/SRAM2b are reserved for the radio core.
|
||||
if chip.starts_with("STM32WB")
|
||||
&& !chip.starts_with("STM32WBA")
|
||||
&& !chip.starts_with("STM32WB0")
|
||||
&& region.starts_with("SRAM2")
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
true
|
||||
}
|
||||
|
||||
@ -16,9 +16,14 @@ use crate::{interrupt, pac, peripherals, Peripheral};
|
||||
const EXTI_COUNT: usize = 16;
|
||||
static EXTI_WAKERS: [AtomicWaker; EXTI_COUNT] = [const { AtomicWaker::new() }; EXTI_COUNT];
|
||||
|
||||
#[cfg(exti_w)]
|
||||
#[cfg(all(exti_w, feature = "_core-cm0p"))]
|
||||
fn cpu_regs() -> pac::exti::Cpu {
|
||||
EXTI.cpu(crate::pac::CORE_INDEX)
|
||||
EXTI.cpu(1)
|
||||
}
|
||||
|
||||
#[cfg(all(exti_w, not(feature = "_core-cm0p")))]
|
||||
fn cpu_regs() -> pac::exti::Cpu {
|
||||
EXTI.cpu(0)
|
||||
}
|
||||
|
||||
#[cfg(not(exti_w))]
|
||||
|
||||
@ -3,12 +3,12 @@ use core::sync::atomic::{fence, Ordering};
|
||||
|
||||
use embassy_hal_internal::drop::OnDrop;
|
||||
use embassy_hal_internal::{into_ref, PeripheralRef};
|
||||
use stm32_metapac::FLASH_BASE;
|
||||
|
||||
use super::{
|
||||
family, Async, Blocking, Error, FlashBank, FlashLayout, FlashRegion, FlashSector, FLASH_SIZE, MAX_ERASE_SIZE,
|
||||
READ_SIZE, WRITE_SIZE,
|
||||
};
|
||||
use crate::_generated::FLASH_BASE;
|
||||
use crate::peripherals::FLASH;
|
||||
use crate::Peripheral;
|
||||
|
||||
|
||||
@ -3,9 +3,9 @@ use core::sync::atomic::{fence, AtomicBool, Ordering};
|
||||
|
||||
use embassy_sync::waitqueue::AtomicWaker;
|
||||
use pac::flash::regs::Sr;
|
||||
use pac::FLASH_SIZE;
|
||||
|
||||
use super::{FlashBank, FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
|
||||
use crate::_generated::FLASH_SIZE;
|
||||
use crate::flash::Error;
|
||||
use crate::pac;
|
||||
#[allow(missing_docs)] // TODO
|
||||
@ -14,9 +14,9 @@ mod alt_regions {
|
||||
use core::marker::PhantomData;
|
||||
|
||||
use embassy_hal_internal::PeripheralRef;
|
||||
use stm32_metapac::FLASH_SIZE;
|
||||
|
||||
use crate::_generated::flash_regions::{BANK1_REGION1, BANK1_REGION2, BANK1_REGION3};
|
||||
use crate::_generated::FLASH_SIZE;
|
||||
use crate::flash::{asynch, Async, Bank1Region1, Bank1Region2, Blocking, Error, Flash, FlashBank, FlashRegion};
|
||||
use crate::peripherals::FLASH;
|
||||
|
||||
|
||||
@ -12,8 +12,7 @@ pub use asynch::InterruptHandler;
|
||||
pub use common::*;
|
||||
|
||||
pub use crate::_generated::flash_regions::*;
|
||||
pub use crate::_generated::MAX_ERASE_SIZE;
|
||||
pub use crate::pac::{FLASH_BASE, FLASH_SIZE, WRITE_SIZE};
|
||||
pub use crate::_generated::{FLASH_BASE, FLASH_SIZE, MAX_ERASE_SIZE, WRITE_SIZE};
|
||||
|
||||
/// Get whether the default flash layout is being used.
|
||||
///
|
||||
|
||||
@ -7,7 +7,7 @@ use critical_section::CriticalSection;
|
||||
use embassy_hal_internal::{impl_peripheral, into_ref, PeripheralRef};
|
||||
|
||||
use crate::pac::gpio::{self, vals};
|
||||
use crate::{pac, peripherals, Peripheral};
|
||||
use crate::{peripherals, Peripheral};
|
||||
|
||||
/// GPIO flexible pin.
|
||||
///
|
||||
@ -726,7 +726,7 @@ pub(crate) trait SealedPin {
|
||||
|
||||
#[inline]
|
||||
fn block(&self) -> gpio::Gpio {
|
||||
pac::GPIO(self._port() as _)
|
||||
crate::_generated::gpio_block(self._port() as _)
|
||||
}
|
||||
|
||||
/// Set the output as high.
|
||||
@ -835,7 +835,7 @@ impl AnyPin {
|
||||
#[cfg(feature = "unstable-pac")]
|
||||
#[inline]
|
||||
pub fn block(&self) -> gpio::Gpio {
|
||||
pac::GPIO(self._port() as _)
|
||||
crate::_generated::gpio_block(self._port() as _)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user