diff --git a/embassy-stm32/src/rcc/h7/mod.rs b/embassy-stm32/src/rcc/h7/mod.rs
index be7f440a1..cd493a80a 100644
--- a/embassy-stm32/src/rcc/h7/mod.rs
+++ b/embassy-stm32/src/rcc/h7/mod.rs
@@ -72,8 +72,6 @@ pub struct Config {
     pub pll1: PllConfig,
     pub pll2: PllConfig,
     pub pll3: PllConfig,
-    pub enable_dma1: bool,
-    pub enable_dma2: bool,
 }
 
 pub struct Rcc<'d> {
@@ -331,14 +329,6 @@ impl<'d> Rcc<'d> {
             });
             while !SYSCFG.cccsr().read().ready() {}
 
-            if self.config.enable_dma1 {
-                RCC.ahb1enr().modify(|w| w.set_dma1en(true));
-            }
-
-            if self.config.enable_dma2 {
-                RCC.ahb1enr().modify(|w| w.set_dma2en(true));
-            }
-
             CoreClocks {
                 hclk: Hertz(rcc_hclk),
                 pclk1: Hertz(rcc_pclk1),
diff --git a/examples/stm32h7/src/bin/camera.rs b/examples/stm32h7/src/bin/camera.rs
index 2fa742b83..d94592071 100644
--- a/examples/stm32h7/src/bin/camera.rs
+++ b/examples/stm32h7/src/bin/camera.rs
@@ -34,8 +34,6 @@ pub fn config() -> Config {
     config.rcc.sys_ck = Some(400.mhz().into());
     config.rcc.hclk = Some(400.mhz().into());
     config.rcc.pll1.q_ck = Some(100.mhz().into());
-    config.rcc.enable_dma1 = true;
-    config.rcc.enable_dma2 = true;
     config.rcc.pclk1 = Some(100.mhz().into());
     config.rcc.pclk2 = Some(100.mhz().into());
     config.rcc.pclk3 = Some(100.mhz().into());
diff --git a/examples/stm32h7/src/example_common.rs b/examples/stm32h7/src/example_common.rs
index 2e26730fa..524bee6d9 100644
--- a/examples/stm32h7/src/example_common.rs
+++ b/examples/stm32h7/src/example_common.rs
@@ -23,6 +23,5 @@ pub fn config() -> Config {
     let mut config = Config::default();
     config.rcc.sys_ck = Some(400.mhz().into());
     config.rcc.pll1.q_ck = Some(100.mhz().into());
-    config.rcc.enable_dma1 = true;
     config
 }