Add io pin masking
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Karun
parent
0b606b57f1
commit
87d2c66ef4
@ -1,3 +1,95 @@
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use core::ops::BitOr;
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/// Pin defines
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#[allow(missing_docs)]
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pub enum TscIOPin {
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Group1Io1,
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Group1Io2,
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Group1Io3,
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Group1Io4,
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Group2Io1,
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Group2Io2,
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Group2Io3,
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Group2Io4,
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Group3Io1,
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Group3Io2,
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Group3Io3,
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Group3Io4,
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Group4Io1,
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Group4Io2,
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Group4Io3,
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Group4Io4,
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Group5Io1,
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Group5Io2,
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Group5Io3,
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Group5Io4,
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Group6Io1,
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Group6Io2,
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Group6Io3,
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Group6Io4,
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Group7Io1,
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Group7Io2,
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Group7Io3,
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Group7Io4,
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Group8Io1,
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Group8Io2,
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Group8Io3,
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Group8Io4,
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}
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impl BitOr<TscIOPin> for u32 {
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type Output = u32;
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fn bitor(self, rhs: TscIOPin) -> Self::Output {
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self | rhs as u32
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}
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}
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impl BitOr for TscIOPin {
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type Output = u32;
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fn bitor(self, rhs: Self) -> Self::Output {
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self as u32 | rhs as u32
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}
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}
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impl Into<u32> for TscIOPin {
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fn into(self) -> u32 {
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match self {
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TscIOPin::Group1Io1 => 0x00000001,
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TscIOPin::Group1Io2 => 0x00000002,
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TscIOPin::Group1Io3 => 0x00000004,
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TscIOPin::Group1Io4 => 0x00000008,
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TscIOPin::Group2Io1 => 0x00000010,
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TscIOPin::Group2Io2 => 0x00000020,
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TscIOPin::Group2Io3 => 0x00000040,
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TscIOPin::Group2Io4 => 0x00000080,
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TscIOPin::Group3Io1 => 0x00000100,
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TscIOPin::Group3Io2 => 0x00000200,
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TscIOPin::Group3Io3 => 0x00000400,
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TscIOPin::Group3Io4 => 0x00000800,
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TscIOPin::Group4Io1 => 0x00001000,
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TscIOPin::Group4Io2 => 0x00002000,
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TscIOPin::Group4Io3 => 0x00004000,
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TscIOPin::Group4Io4 => 0x00008000,
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TscIOPin::Group5Io1 => 0x00010000,
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TscIOPin::Group5Io2 => 0x00020000,
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TscIOPin::Group5Io3 => 0x00040000,
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TscIOPin::Group5Io4 => 0x00080000,
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TscIOPin::Group6Io1 => 0x00100000,
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TscIOPin::Group6Io2 => 0x00200000,
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TscIOPin::Group6Io3 => 0x00400000,
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TscIOPin::Group6Io4 => 0x00800000,
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TscIOPin::Group7Io1 => 0x01000000,
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TscIOPin::Group7Io2 => 0x02000000,
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TscIOPin::Group7Io3 => 0x04000000,
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TscIOPin::Group7Io4 => 0x08000000,
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TscIOPin::Group8Io1 => 0x10000000,
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TscIOPin::Group8Io2 => 0x20000000,
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TscIOPin::Group8Io3 => 0x40000000,
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TscIOPin::Group8Io4 => 0x80000000,
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}
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}
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}
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/// Charge transfer pulse cycles
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#[allow(missing_docs)]
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#[derive(Copy, Clone)]
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@ -6,12 +6,15 @@
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pub mod enums;
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use crate::gpio::AnyPin;
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use crate::pac::tsc::regs;
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use crate::{pac::tsc::Tsc as Regs, rcc::RccPeripheral};
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use crate::{peripherals, Peripheral};
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use embassy_hal_internal::{into_ref, PeripheralRef};
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pub use enums::*;
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const TSC_NUM_GROUPS: u32 = 8;
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/// Error type defined for TSC
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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@ -110,6 +113,12 @@ pub struct Config {
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pub acquisition_mode: bool,
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/// Enable max count interrupt
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pub max_count_interrupt: bool,
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/// Channel IO mask
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pub channel_ios: u32,
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/// Shield IO mask
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pub shield_ios: u32,
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/// Sampling IO mask
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pub sampling_ios: u32,
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}
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impl Default for Config {
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@ -126,6 +135,9 @@ impl Default for Config {
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synchro_pin_polarity: false,
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acquisition_mode: false,
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max_count_interrupt: false,
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channel_ios: 0,
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shield_ios: 0,
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sampling_ios: 0,
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}
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}
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}
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@ -175,45 +187,44 @@ impl<'d, T: Instance> Tsc<'d, T> {
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pub fn new(
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peri: impl Peripheral<P = T> + 'd,
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// g1_d1: Option<PeriPin<impl Peripheral<P = impl G1IO1Pin<T>> + 'd>>,
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g1_d2: Option<PeriPin<impl Peripheral<P = impl G1IO2Pin<T>> + 'd>>,
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g1_d3: Option<PeriPin<impl Peripheral<P = impl G1IO3Pin<T>> + 'd>>,
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g1_d4: Option<impl Peripheral<P = impl G1IO4Pin<T>> + 'd>,
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// g1_d2: Option<PeriPin<impl Peripheral<P = impl G1IO2Pin<T>> + 'd>>,
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// g1_d3: Option<PeriPin<impl Peripheral<P = impl G1IO3Pin<T>> + 'd>>,
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// g1_d4: Option<PeriPin<impl Peripheral<P = impl G1IO4Pin<T>> + 'd>>,
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g2_d1: Option<impl Peripheral<P = impl G2IO1Pin<T>> + 'd>,
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g2_d2: Option<impl Peripheral<P = impl G2IO2Pin<T>> + 'd>,
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g2_d3: Option<impl Peripheral<P = impl G2IO3Pin<T>> + 'd>,
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g2_d4: Option<impl Peripheral<P = impl G2IO4Pin<T>> + 'd>,
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// g2_d1: Option<impl Peripheral<P = impl G2IO1Pin<T>> + 'd>,
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// g2_d2: Option<impl Peripheral<P = impl G2IO2Pin<T>> + 'd>,
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// g2_d3: Option<impl Peripheral<P = impl G2IO3Pin<T>> + 'd>,
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// g2_d4: Option<impl Peripheral<P = impl G2IO4Pin<T>> + 'd>,
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g3_d1: Option<impl Peripheral<P = impl G3IO1Pin<T>> + 'd>,
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g3_d2: Option<impl Peripheral<P = impl G3IO2Pin<T>> + 'd>,
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g3_d3: Option<impl Peripheral<P = impl G3IO3Pin<T>> + 'd>,
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g3_d4: Option<impl Peripheral<P = impl G3IO4Pin<T>> + 'd>,
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// g3_d1: Option<impl Peripheral<P = impl G3IO1Pin<T>> + 'd>,
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// g3_d2: Option<impl Peripheral<P = impl G3IO2Pin<T>> + 'd>,
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// g3_d3: Option<impl Peripheral<P = impl G3IO3Pin<T>> + 'd>,
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// g3_d4: Option<impl Peripheral<P = impl G3IO4Pin<T>> + 'd>,
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g4_d1: Option<impl Peripheral<P = impl G4IO1Pin<T>> + 'd>,
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g4_d2: Option<impl Peripheral<P = impl G4IO2Pin<T>> + 'd>,
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g4_d3: Option<impl Peripheral<P = impl G4IO3Pin<T>> + 'd>,
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g4_d4: Option<impl Peripheral<P = impl G4IO4Pin<T>> + 'd>,
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// g4_d1: Option<impl Peripheral<P = impl G4IO1Pin<T>> + 'd>,
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// g4_d2: Option<impl Peripheral<P = impl G4IO2Pin<T>> + 'd>,
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// g4_d3: Option<impl Peripheral<P = impl G4IO3Pin<T>> + 'd>,
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// g4_d4: Option<impl Peripheral<P = impl G4IO4Pin<T>> + 'd>,
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g5_d1: Option<impl Peripheral<P = impl G5IO1Pin<T>> + 'd>,
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g5_d2: Option<impl Peripheral<P = impl G5IO2Pin<T>> + 'd>,
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g5_d3: Option<impl Peripheral<P = impl G5IO3Pin<T>> + 'd>,
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g5_d4: Option<impl Peripheral<P = impl G5IO4Pin<T>> + 'd>,
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// g5_d1: Option<impl Peripheral<P = impl G5IO1Pin<T>> + 'd>,
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// g5_d2: Option<impl Peripheral<P = impl G5IO2Pin<T>> + 'd>,
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// g5_d3: Option<impl Peripheral<P = impl G5IO3Pin<T>> + 'd>,
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// g5_d4: Option<impl Peripheral<P = impl G5IO4Pin<T>> + 'd>,
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g6_d1: Option<impl Peripheral<P = impl G6IO1Pin<T>> + 'd>,
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g6_d2: Option<impl Peripheral<P = impl G6IO2Pin<T>> + 'd>,
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g6_d3: Option<impl Peripheral<P = impl G6IO3Pin<T>> + 'd>,
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g6_d4: Option<impl Peripheral<P = impl G6IO4Pin<T>> + 'd>,
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// g6_d1: Option<impl Peripheral<P = impl G6IO1Pin<T>> + 'd>,
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// g6_d2: Option<impl Peripheral<P = impl G6IO2Pin<T>> + 'd>,
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// g6_d3: Option<impl Peripheral<P = impl G6IO3Pin<T>> + 'd>,
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// g6_d4: Option<impl Peripheral<P = impl G6IO4Pin<T>> + 'd>,
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g7_d1: Option<impl Peripheral<P = impl G7IO1Pin<T>> + 'd>,
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g7_d2: Option<impl Peripheral<P = impl G7IO2Pin<T>> + 'd>,
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g7_d3: Option<impl Peripheral<P = impl G7IO3Pin<T>> + 'd>,
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g7_d4: Option<impl Peripheral<P = impl G7IO4Pin<T>> + 'd>,
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g8_d1: Option<impl Peripheral<P = impl G8IO1Pin<T>> + 'd>,
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g8_d2: Option<impl Peripheral<P = impl G8IO2Pin<T>> + 'd>,
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g8_d3: Option<impl Peripheral<P = impl G8IO3Pin<T>> + 'd>,
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g8_d4: Option<impl Peripheral<P = impl G8IO4Pin<T>> + 'd>,
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// g7_d1: Option<impl Peripheral<P = impl G7IO1Pin<T>> + 'd>,
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// g7_d2: Option<impl Peripheral<P = impl G7IO2Pin<T>> + 'd>,
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// g7_d3: Option<impl Peripheral<P = impl G7IO3Pin<T>> + 'd>,
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// g7_d4: Option<impl Peripheral<P = impl G7IO4Pin<T>> + 'd>,
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// g8_d1: Option<impl Peripheral<P = impl G8IO1Pin<T>> + 'd>,
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// g8_d2: Option<impl Peripheral<P = impl G8IO2Pin<T>> + 'd>,
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// g8_d3: Option<impl Peripheral<P = impl G8IO3Pin<T>> + 'd>,
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// g8_d4: Option<impl Peripheral<P = impl G8IO4Pin<T>> + 'd>,
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config: Config,
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) -> Self {
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into_ref!(peri);
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@ -224,6 +235,15 @@ impl<'d, T: Instance> Tsc<'d, T> {
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}
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// fn filter_group() -> Option<PinGroup<'d>> {}
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fn extract_groups(io_mask: u32) -> u32 {
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let mut groups: u32 = 0;
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for idx in 0..TSC_NUM_GROUPS {
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if io_mask & (0x0F << idx * 4) != 0 {
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groups |= 1 << idx
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}
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}
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groups
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}
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fn new_inner(peri: impl Peripheral<P = T> + 'd, config: Config) -> Self {
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into_ref!(peri);
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@ -245,22 +265,20 @@ impl<'d, T: Instance> Tsc<'d, T> {
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// Set IO configuration
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// Disable Schmitt trigger hysteresis on all used TSC IOs
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// T::REGS.iohcr().modify(|w| {
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// w.
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// });
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T::REGS
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.iohcr()
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.write(|w| w.0 = config.channel_ios | config.shield_ios | config.sampling_ios);
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// Set channel and shield IOs
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// T::REGS.ioccr().modify(|w| {});
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T::REGS.ioccr().write(|w| w.0 = config.channel_ios | config.shield_ios);
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// Set sampling IOs
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// T::REGS.ioscr().modify(|w| {
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// w.set_g1_io1(val)
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// });
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T::REGS.ioscr().write(|w| w.0 = config.sampling_ios);
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// Set the groups to be acquired
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// T::REGS.iogcsr().modify(|w| {
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// w.set_g1e(val);
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// });
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T::REGS
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.iogcsr()
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.write(|w| w.0 = Self::extract_groups(config.channel_ios));
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// Disable interrupts
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T::REGS.ier().modify(|w| {
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