LailaTheElf/embassy
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Fix build

Browse Source
This commit is contained in:
Eli Orona 2024-02-16 16:45:58 -08:00 committed by GitHub
parent 77739faaeb
commit 7592e8be6e
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
1 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
embassy-stm32/src/rcc/f013.rs
View File

@ -495,7 +495,7 @@ pub(crate) unsafe fn init(config: Config) {
TimClockSource::PClk2 => {} TimClockSource::PClk2 => {}
TimClockSource::PllClk => { TimClockSource::PllClk => {
RCC.cfgr3() RCC.cfgr3()
.modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Timsw::PLL1_P)); .modify(|w| w.set_tim2sw(crate::pac::rcc::vals::Tim2sw::PLL1_P));
} }
}; };
@ -533,7 +533,7 @@ pub(crate) unsafe fn init(config: Config) {
stm32f398 stm32f398
))] ))]
match config.tim.tim15 { match config.tim.tim15 {
TimClockSource::PClk2 => None, TimClockSource::PClk2 => {},
TimClockSource::PllClk => { TimClockSource::PllClk => {
RCC.cfgr3() RCC.cfgr3()
.modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P)); .modify(|w| w.set_tim15sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@ -548,7 +548,7 @@ pub(crate) unsafe fn init(config: Config) {
stm32f398 stm32f398
))] ))]
match config.tim.tim16 { match config.tim.tim16 {
TimClockSource::PClk2 => None, TimClockSource::PClk2 => {},
TimClockSource::PllClk => { TimClockSource::PllClk => {
RCC.cfgr3() RCC.cfgr3()
.modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P)); .modify(|w| w.set_tim16sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@ -563,7 +563,7 @@ pub(crate) unsafe fn init(config: Config) {
stm32f398 stm32f398
))] ))]
match config.tim.tim17 { match config.tim.tim17 {
TimClockSource::PClk2 => None, TimClockSource::PClk2 => {},
TimClockSource::PllClk => { TimClockSource::PllClk => {
RCC.cfgr3() RCC.cfgr3()
.modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P)); .modify(|w| w.set_tim17sw(crate::pac::rcc::vals::Timsw::PLL1_P));
@ -572,7 +572,7 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(any(all(stm32f303, any(package_D, package_E))))] #[cfg(any(all(stm32f303, any(package_D, package_E))))]
match config.tim.tim20 { match config.tim.tim20 {
TimClockSource::PClk2 => None, TimClockSource::PClk2 => {},
TimClockSource::PllClk => { TimClockSource::PllClk => {
RCC.cfgr3() RCC.cfgr3()
.modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P)); .modify(|w| w.set_tim20sw(crate::pac::rcc::vals::Timsw::PLL1_P));