stm32/usart: move init code to function that's not generic in T
This commit is contained in:
Jan Špaček
parent
44e4a2c9e9
commit
664e4a5c03
@ -16,9 +16,7 @@ use super::{
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Regs, RtsPin, RxPin, TxPin,
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};
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use crate::gpio::{AFType, AnyPin, SealedPin as _};
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use crate::interrupt::typelevel::Interrupt as _;
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use crate::interrupt::{self, InterruptExt};
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use crate::rcc;
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use crate::time::Hertz;
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/// Interrupt handler.
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@ -284,35 +282,11 @@ impl<'d> BufferedUart<'d> {
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rx_buffer: &'d mut [u8],
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config: Config,
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) -> Result<Self, ConfigError> {
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rcc::enable_and_reset::<T>();
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let info = T::info();
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let state = T::buffered_state();
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let kernel_clock = T::frequency();
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let len = tx_buffer.len();
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unsafe { state.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
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let len = rx_buffer.len();
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unsafe { state.rx_buf.init(rx_buffer.as_mut_ptr(), len) };
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info.regs.cr3().write(|w| {
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w.set_rtse(rts.is_some());
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w.set_ctse(cts.is_some());
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#[cfg(not(any(usart_v1, usart_v2)))]
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w.set_dem(de.is_some());
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});
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configure(info, kernel_clock, &config, true, true)?;
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info.regs.cr1().modify(|w| {
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w.set_rxneie(true);
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w.set_idleie(true);
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});
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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state.tx_rx_refcount.store(2, Ordering::Relaxed);
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Ok(Self {
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let mut this = Self {
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rx: BufferedUartRx {
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info,
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state,
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@ -328,7 +302,45 @@ impl<'d> BufferedUart<'d> {
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cts,
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de,
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},
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})
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};
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this.enable_and_configure(tx_buffer, rx_buffer, &config)?;
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Ok(this)
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}
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fn enable_and_configure(
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&mut self,
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tx_buffer: &'d mut [u8],
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rx_buffer: &'d mut [u8],
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config: &Config,
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) -> Result<(), ConfigError> {
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let info = self.rx.info;
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let state = self.rx.state;
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info.rcc.enable_and_reset();
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let len = tx_buffer.len();
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unsafe { state.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
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let len = rx_buffer.len();
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unsafe { state.rx_buf.init(rx_buffer.as_mut_ptr(), len) };
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info.regs.cr3().write(|w| {
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w.set_rtse(self.rx.rts.is_some());
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w.set_ctse(self.tx.cts.is_some());
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#[cfg(not(any(usart_v1, usart_v2)))]
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w.set_dem(self.tx.de.is_some());
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});
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configure(info, self.rx.kernel_clock, &config, true, true)?;
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info.regs.cr1().modify(|w| {
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w.set_rxneie(true);
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w.set_idleie(true);
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});
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info.interrupt.unpend();
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unsafe { info.interrupt.enable() };
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state.tx_rx_refcount.store(2, Ordering::Relaxed);
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Ok(())
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}
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/// Split the driver into a Tx and Rx part (useful for sending to separate tasks)
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@ -28,7 +28,7 @@ use crate::pac::usart::Lpuart as Regs;
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#[cfg(any(usart_v1, usart_v2))]
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use crate::pac::usart::Usart as Regs;
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use crate::pac::usart::{regs, vals};
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use crate::rcc::{self, RccInfo, SealedRccPeripheral};
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use crate::rcc::{RccInfo, SealedRccPeripheral};
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use crate::time::Hertz;
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use crate::Peripheral;
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@ -429,29 +429,33 @@ impl<'d, M: Mode> UartTx<'d, M> {
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tx_dma: Option<ChannelAndRequest<'d>>,
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config: Config,
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) -> Result<Self, ConfigError> {
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rcc::enable_and_reset::<T>();
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let info = T::info();
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let state = T::state();
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let kernel_clock = T::frequency();
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let r = info.regs;
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r.cr3().modify(|w| {
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w.set_ctse(cts.is_some());
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});
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configure(info, kernel_clock, &config, false, true)?;
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state.tx_rx_refcount.store(1, Ordering::Relaxed);
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Ok(Self {
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info,
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state,
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kernel_clock,
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let mut this = Self {
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info: T::info(),
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state: T::state(),
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kernel_clock: T::frequency(),
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tx,
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cts,
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de: None,
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tx_dma,
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_phantom: PhantomData,
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})
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};
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this.enable_and_configure(&config)?;
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Ok(this)
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}
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fn enable_and_configure(&mut self, config: &Config) -> Result<(), ConfigError> {
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let info = self.info;
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let state = self.state;
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info.rcc.enable_and_reset();
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info.regs.cr3().modify(|w| {
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w.set_ctse(self.cts.is_some());
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});
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configure(info, self.kernel_clock, config, false, true)?;
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state.tx_rx_refcount.store(1, Ordering::Relaxed);
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Ok(())
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}
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/// Reconfigure the driver
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@ -775,34 +779,38 @@ impl<'d, M: Mode> UartRx<'d, M> {
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rx_dma: Option<ChannelAndRequest<'d>>,
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config: Config,
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) -> Result<Self, ConfigError> {
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rcc::enable_and_reset::<T>();
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let info = T::info();
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let state = T::state();
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let kernel_clock = T::frequency();
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let r = info.regs;
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r.cr3().write(|w| {
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w.set_rtse(rts.is_some());
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});
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configure(info, kernel_clock, &config, true, false)?;
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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state.tx_rx_refcount.store(1, Ordering::Relaxed);
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Ok(Self {
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let mut this = Self {
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_phantom: PhantomData,
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info,
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state,
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kernel_clock,
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info: T::info(),
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state: T::state(),
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kernel_clock: T::frequency(),
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rx,
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rts,
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rx_dma,
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detect_previous_overrun: config.detect_previous_overrun,
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#[cfg(any(usart_v1, usart_v2))]
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buffered_sr: stm32_metapac::usart::regs::Sr(0),
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})
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};
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this.enable_and_configure(&config)?;
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Ok(this)
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}
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fn enable_and_configure(&mut self, config: &Config) -> Result<(), ConfigError> {
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let info = self.info;
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let state = self.state;
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info.rcc.enable_and_reset();
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info.regs.cr3().write(|w| {
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w.set_rtse(self.rts.is_some());
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});
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configure(info, self.kernel_clock, &config, true, false)?;
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info.interrupt.unpend();
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unsafe { info.interrupt.enable() };
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state.tx_rx_refcount.store(1, Ordering::Relaxed);
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Ok(())
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}
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/// Reconfigure the driver
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@ -1228,26 +1236,11 @@ impl<'d, M: Mode> Uart<'d, M> {
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rx_dma: Option<ChannelAndRequest<'d>>,
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config: Config,
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) -> Result<Self, ConfigError> {
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rcc::enable_and_reset::<T>();
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let info = T::info();
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let state = T::state();
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let kernel_clock = T::frequency();
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info.regs.cr3().write(|w| {
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w.set_rtse(rts.is_some());
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w.set_ctse(cts.is_some());
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#[cfg(not(any(usart_v1, usart_v2)))]
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w.set_dem(de.is_some());
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});
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configure(info, kernel_clock, &config, true, true)?;
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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state.tx_rx_refcount.store(2, Ordering::Relaxed);
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Ok(Self {
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let mut this = Self {
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tx: UartTx {
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_phantom: PhantomData,
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info,
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@ -1270,7 +1263,30 @@ impl<'d, M: Mode> Uart<'d, M> {
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#[cfg(any(usart_v1, usart_v2))]
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buffered_sr: stm32_metapac::usart::regs::Sr(0),
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},
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})
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};
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this.enable_and_configure(&config)?;
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Ok(this)
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}
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fn enable_and_configure(&mut self, config: &Config) -> Result<(), ConfigError> {
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let info = self.rx.info;
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let state = self.rx.state;
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info.rcc.enable_and_reset();
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info.regs.cr3().write(|w| {
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w.set_rtse(self.rx.rts.is_some());
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w.set_ctse(self.tx.cts.is_some());
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#[cfg(not(any(usart_v1, usart_v2)))]
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w.set_dem(self.tx.de.is_some());
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});
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configure(info, self.rx.kernel_clock, config, true, true)?;
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info.interrupt.unpend();
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unsafe { info.interrupt.enable() };
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state.tx_rx_refcount.store(2, Ordering::Relaxed);
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Ok(())
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}
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/// Perform a blocking write
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