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stm32: xspi fixes and consistency

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Fix some incorrect DTR flags, fix _bit vs _Bit inconsistency (copied
from qspi and ospi).

Use the same NCS pullup for all constructors.

xspi is now enabled in PWR register
This commit is contained in:
Matt Johnston 2025-04-04 15:41:35 +08:00
parent 6b80f3bada
commit 5f7da4cfc8
2 changed files with 25 additions and 12 deletions
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8
embassy-stm32/src/xspi/enums.rs
View File

@ -160,9 +160,9 @@ impl Into<u8> for MemorySize {
#[derive(Copy, Clone)]
pub enum AddressSize {
/// 8-bit address
_8Bit,
_8bit,
/// 16-bit address
_16Bit,
_16bit,
/// 24-bit address
_24bit,
/// 32-bit address
@ -172,8 +172,8 @@ pub enum AddressSize {
impl Into<u8> for AddressSize {
fn into(self) -> u8 {
match self {
AddressSize::_8Bit => 0b00,
AddressSize::_16Bit => 0b01,
AddressSize::_8bit => 0b00,
AddressSize::_16bit => 0b01,
AddressSize::_24bit => 0b10,
AddressSize::_32bit => 0b11,
}

29
embassy-stm32/src/xspi/mod.rs
View File

@ -122,17 +122,17 @@ impl Default for TransferConfig {
Self {
iwidth: XspiWidth::NONE,
instruction: None,
isize: AddressSize::_8Bit,
isize: AddressSize::_8bit,
idtr: false,
adwidth: XspiWidth::NONE,
address: None,
adsize: AddressSize::_8Bit,
adsize: AddressSize::_8bit,
addtr: false,
abwidth: XspiWidth::NONE,
alternate_bytes: None,
absize: AddressSize::_8Bit,
absize: AddressSize::_8bit,
abdtr: false,
dwidth: XspiWidth::NONE,
@ -214,11 +214,11 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> {
w.set_isize(WccrIsize::from_bits(write_config.isize.into()));
w.set_admode(WccrAdmode::from_bits(write_config.adwidth.into()));
w.set_addtr(write_config.idtr);
w.set_addtr(write_config.addtr);
w.set_adsize(WccrAdsize::from_bits(write_config.adsize.into()));
w.set_dmode(WccrDmode::from_bits(write_config.dwidth.into()));
w.set_ddtr(write_config.idtr);
w.set_ddtr(write_config.ddtr);
w.set_abmode(WccrAbmode::from_bits(write_config.abwidth.into()));
w.set_dqse(true);
@ -283,6 +283,13 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> {
width: XspiWidth,
dual_quad: bool,
) -> Self {
// Enable the interface
match T::SPI_IDX {
1 => crate::pac::PWR.csr2().modify(|r| r.set_en_xspim1(true)),
2 => crate::pac::PWR.csr2().modify(|r| r.set_en_xspim2(true)),
_ => unreachable!(),
};
#[cfg(xspim_v1)]
{
// RCC for xspim should be enabled before writing register
@ -447,7 +454,7 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> {
w.set_isize(CcrIsize::from_bits(command.isize.into()));
w.set_admode(CcrAdmode::from_bits(command.adwidth.into()));
w.set_addtr(command.idtr);
w.set_addtr(command.addtr);
w.set_adsize(CcrAdsize::from_bits(command.adsize.into()));
w.set_dmode(CcrDmode::from_bits(command.dwidth.into()));
@ -686,7 +693,10 @@ impl<'d, T: Instance> Xspi<'d, T, Blocking> {
None,
new_pin!(clk, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
ncs.sel(),
new_pin!(ncs, AfType::output(OutputType::OpenDrain, Speed::VeryHigh)),
new_pin!(
ncs,
AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
),
None,
None,
None,
@ -915,7 +925,10 @@ impl<'d, T: Instance> Xspi<'d, T, Async> {
None,
new_pin!(clk, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
ncs.sel(),
new_pin!(ncs, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
new_pin!(
ncs,
AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
),
None,
None,
None,