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Expose async functions for QSPI

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This commit is contained in:
Dion Dokter 2024-10-29 17:13:09 +01:00
parent 4f08d5bc5f
commit 5db6b4874d
1 changed files with 28 additions and 4 deletions
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32
embassy-stm32/src/qspi/mod.rs
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@ -353,6 +353,21 @@ impl<'d, T: Instance> Qspi<'d, T, Async> {
/// Blocking read data, using DMA. /// Blocking read data, using DMA.
pub fn blocking_read_dma(&mut self, buf: &mut [u8], transaction: TransferConfig) { pub fn blocking_read_dma(&mut self, buf: &mut [u8], transaction: TransferConfig) {
let transfer = self.start_read_transfer(transaction, buf);
transfer.blocking_wait();
}
/// Blocking read data, using DMA.
pub async fn read_dma(&mut self, buf: &mut [u8], transaction: TransferConfig) {
let transfer = self.start_read_transfer(transaction, buf);
transfer.await;
}
fn start_read_transfer<'a>(
&'a mut self,
transaction: TransferConfig,
buf: &'a mut [u8],
) -> crate::dma::Transfer<'a> {
self.setup_transaction(QspiMode::IndirectWrite, &transaction, Some(buf.len())); self.setup_transaction(QspiMode::IndirectWrite, &transaction, Some(buf.len()));
T::REGS.ccr().modify(|v| { T::REGS.ccr().modify(|v| {
@ -373,12 +388,22 @@ impl<'d, T: Instance> Qspi<'d, T, Async> {
// STM32H7 does not have dmaen // STM32H7 does not have dmaen
#[cfg(not(stm32h7))] #[cfg(not(stm32h7))]
T::REGS.cr().modify(|v| v.set_dmaen(true)); T::REGS.cr().modify(|v| v.set_dmaen(true));
transfer
transfer.blocking_wait();
} }
/// Blocking write data, using DMA. /// Blocking write data, using DMA.
pub fn blocking_write_dma(&mut self, buf: &[u8], transaction: TransferConfig) { pub fn blocking_write_dma(&mut self, buf: &[u8], transaction: TransferConfig) {
let transfer = self.start_write_transfer(transaction, buf);
transfer.blocking_wait();
}
/// Async write data, using DMA.
pub async fn write_dma(&mut self, buf: &[u8], transaction: TransferConfig) {
let transfer = self.start_write_transfer(transaction, buf);
transfer.await;
}
fn start_write_transfer<'a>(&'a mut self, transaction: TransferConfig, buf: &'a [u8]) -> crate::dma::Transfer<'a> {
self.setup_transaction(QspiMode::IndirectWrite, &transaction, Some(buf.len())); self.setup_transaction(QspiMode::IndirectWrite, &transaction, Some(buf.len()));
T::REGS.ccr().modify(|v| { T::REGS.ccr().modify(|v| {
@ -395,8 +420,7 @@ impl<'d, T: Instance> Qspi<'d, T, Async> {
// STM32H7 does not have dmaen // STM32H7 does not have dmaen
#[cfg(not(stm32h7))] #[cfg(not(stm32h7))]
T::REGS.cr().modify(|v| v.set_dmaen(true)); T::REGS.cr().modify(|v| v.set_dmaen(true));
transfer
transfer.blocking_wait();
} }
} }