Some small improvements
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@ -27,8 +27,9 @@ impl<'a, PIO: Instance> PioOneWireProgram<'a, PIO> {
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.origin 0
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.origin 0
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; Tick rate is 1 tick per 6us, so all delays should be calculated back to that
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; Tick rate is 1 tick per 6us, so all delays should be calculated back to that
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; All the instructions have a calculated delay in [], -1 for the instruction
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; All the instructions have a calculated delay XX in us as [(XX / CLK) - 1].
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; The delay also be 0 which will take 6us for the instruction itself
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; The - 1 is for the instruction which also takes one clock cyle.
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; The delay can be 0 which will result in just 6us for the instruction itself
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.define CLK 6
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.define CLK 6
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; Write the reset block after trigger
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; Write the reset block after trigger
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@ -98,16 +99,13 @@ impl<'d, PIO: Instance, const SM: usize> PioOneWire<'d, PIO, SM> {
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cfg.use_program(&program.prg, &[&pin]);
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cfg.use_program(&program.prg, &[&pin]);
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cfg.set_in_pins(&[&pin]);
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cfg.set_in_pins(&[&pin]);
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cfg.shift_in = ShiftConfig {
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let shift_cfg = ShiftConfig {
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auto_fill: true,
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direction: ShiftDirection::Right,
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threshold: 8,
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};
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cfg.shift_out = ShiftConfig {
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auto_fill: true,
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auto_fill: true,
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direction: ShiftDirection::Right,
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direction: ShiftDirection::Right,
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threshold: 8,
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threshold: 8,
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};
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};
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cfg.shift_in = shift_cfg;
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cfg.shift_out = shift_cfg;
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let divider = (clk_sys_freq() / 1000000) as u16 * 6;
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let divider = (clk_sys_freq() / 1000000) as u16 * 6;
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cfg.clock_divider = divider.into();
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cfg.clock_divider = divider.into();
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