add async read for u5 ADC4
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d169249482
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4f4740eeb2
@ -4,13 +4,14 @@ pub use crate::pac::adc::vals::Adc4Presc as Presc;
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pub use crate::pac::adc::regs::Adc4Chselrmod0;
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pub use crate::pac::adc::regs::Adc4Chselrmod0;
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#[allow(unused)]
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#[allow(unused)]
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use pac::adc::vals::{Adc4Exten, Adc4OversamplingRatio};
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use pac::adc::vals::{Adc4Exten, Adc4OversamplingRatio, Adc4Dmacfg};
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use super::{
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use super::{
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blocking_delay_us, AdcChannel, SealedAdcChannel
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blocking_delay_us, AdcChannel, SealedAdcChannel, AnyAdcChannel, RxDma4
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};
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};
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use crate::time::Hertz;
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use crate::time::Hertz;
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use crate::{pac, rcc, Peripheral};
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use crate::{pac, rcc, Peripheral};
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use crate::dma::Transfer;
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const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(55);
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const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(55);
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@ -182,6 +183,12 @@ pub struct Adc4<'d, T: Instance> {
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adc: crate::PeripheralRef<'d, T>,
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adc: crate::PeripheralRef<'d, T>,
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}
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}
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#[derive(Debug)]
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pub enum Adc4Error {
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InvalidSequence,
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DMAError
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}
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impl<'d, T: Instance> Adc4<'d, T> {
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impl<'d, T: Instance> Adc4<'d, T> {
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/// Create a new ADC driver.
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/// Create a new ADC driver.
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pub fn new(adc: impl Peripheral<P = T> + 'd) -> Self {
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pub fn new(adc: impl Peripheral<P = T> + 'd) -> Self {
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@ -244,6 +251,7 @@ impl<'d, T: Instance> Adc4<'d, T> {
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// single conversion mode, software trigger
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// single conversion mode, software trigger
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T::regs().cfgr1().modify(|w| {
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T::regs().cfgr1().modify(|w| {
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w.set_cont(false);
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w.set_cont(false);
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w.set_discen(false);
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w.set_exten(Adc4Exten::DISABLED);
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w.set_exten(Adc4Exten::DISABLED);
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});
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});
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@ -336,8 +344,18 @@ impl<'d, T: Instance> Adc4<'d, T> {
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})
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})
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}
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}
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/// Perform a single conversion.
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/// Read an ADC channel.
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fn convert(&mut self) -> u16 {
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pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16{
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channel.setup();
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T::regs().cfgr1().modify(|reg| {
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reg.set_chselrmod(false);
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});
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T::regs().chselrmod0().write_value(Adc4Chselrmod0(0_u32));
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T::regs().chselrmod0().modify(|w| {
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w.set_chsel(channel.channel() as usize, true);
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});
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T::regs().isr().modify(|reg| {
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T::regs().isr().modify(|reg| {
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reg.set_eos(true);
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reg.set_eos(true);
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reg.set_eoc(true);
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reg.set_eoc(true);
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@ -355,22 +373,92 @@ impl<'d, T: Instance> Adc4<'d, T> {
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T::regs().dr().read().0 as u16
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T::regs().dr().read().0 as u16
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}
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}
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/// Read an ADC channel.
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/// Channels can not be repeated and must be in ascending order!
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pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
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/// TODO: broken
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self.read_channel(channel)
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pub async fn read(
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}
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&mut self,
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rx_dma: &mut impl RxDma4<T>,
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sequence: impl ExactSizeIterator<Item = &mut AnyAdcChannel<T>>,
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readings: &mut [u16],
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) -> Result<(), Adc4Error> {
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assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
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assert!(
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sequence.len() == readings.len(),
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"Sequence length must be equal to readings length"
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);
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fn configure_channel(channel: &mut impl AdcChannel<T>) {
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// Ensure no conversions are ongoing
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channel.setup();
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Self::cancel_conversions();
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T::regs().chselrmod0().write_value(Adc4Chselrmod0(0_u32));
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T::regs().chselrmod0().modify(|w| {
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T::regs().isr().modify(|reg| {
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w.set_chsel(channel.channel() as usize, true);
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reg.set_ovr(true);
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reg.set_eos(true);
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reg.set_eoc(true);
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});
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});
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T::regs().cfgr1().modify(|reg| {
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reg.set_dmaen(true);
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reg.set_dmacfg(Adc4Dmacfg::ONESHOT);
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reg.set_chselrmod(false);
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});
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let mut prev_channel: i16 = -1;
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T::regs().chselrmod0().write_value(Adc4Chselrmod0(0_u32));
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for channel in sequence {
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let channel_num = channel.channel;
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if channel_num as i16 <= prev_channel {
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return Err(Adc4Error::InvalidSequence);
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};
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prev_channel = channel_num as i16;
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T::regs().chselrmod0().modify(|w| {
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w.set_chsel(channel.channel as usize, true);
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});
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};
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let request = rx_dma.request();
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let transfer = unsafe {
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Transfer::new_read(
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rx_dma,
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request,
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T::regs().dr().as_ptr() as *mut u16,
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readings,
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Default::default(),
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)
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};
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// Start conversion
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T::regs().cr().modify(|reg| {
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reg.set_adstart(true);
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});
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// Wait for conversion sequence to finish.
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transfer.await;
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blocking_delay_us(10);
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// Ensure conversions are finished.
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Self::cancel_conversions();
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// Reset configuration.
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T::regs().cfgr1().modify(|reg| {
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reg.set_dmaen(false);
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});
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if T::regs().isr().read().ovr() {
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Err(Adc4Error::DMAError)
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} else {
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Ok(())
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}
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}
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}
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fn read_channel(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
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fn cancel_conversions() {
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Self::configure_channel(channel);
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if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
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let ret = self.convert();
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T::regs().cr().modify(|reg| {
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ret
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reg.set_adstp(true);
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});
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while T::regs().cr().read().adstart() {}
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}
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}
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}
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}
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}
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@ -36,55 +36,99 @@ async fn main(spawner: embassy_executor::Spawner) {
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let mut p = embassy_stm32::init(config);
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let mut p = embassy_stm32::init(config);
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let mut adc = adc::Adc::new(p.ADC1);
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// **** ADC1 init ****
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let mut adc_pin1 = p.PA3; // A0 on nucleo u5a5
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let mut adc1 = adc::Adc::new(p.ADC1);
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let mut adc_pin2 = p.PA2; // A1 on nucleo u5a5
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let mut adc1_pin1 = p.PA3; // A0 on nucleo u5a5
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adc.set_resolution(adc::Resolution::BITS14);
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let mut adc1_pin2 = p.PA2; // A1
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adc.set_averaging(adc::Averaging::Samples1024);
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adc1.set_resolution(adc::Resolution::BITS14);
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adc.set_sample_time(adc::SampleTime::CYCLES160_5);
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adc1.set_averaging(adc::Averaging::Samples1024);
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let max = adc::resolution_to_max_count(adc::Resolution::BITS14);
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adc1.set_sample_time(adc::SampleTime::CYCLES160_5);
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let max1 = adc::resolution_to_max_count(adc::Resolution::BITS14);
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// **** ADC2 init ****
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let mut adc2 = adc::Adc::new(p.ADC2);
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let mut adc2_pin1 = p.PC3; // A2
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let mut adc2_pin2 = p.PB0; // A3
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adc2.set_resolution(adc::Resolution::BITS14);
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adc2.set_averaging(adc::Averaging::Samples1024);
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adc2.set_sample_time(adc::SampleTime::CYCLES160_5);
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let max2 = adc::resolution_to_max_count(adc::Resolution::BITS14);
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// **** ADC4 init ****
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let mut adc4 = adc4::Adc4::new(p.ADC4);
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let mut adc4 = adc4::Adc4::new(p.ADC4);
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let mut adc4_pin1 = p.PD11;
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let mut adc4_pin1 = p.PC1; // A4
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let mut adc4_pin2 = p.PC0;
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let mut adc4_pin2 = p.PC0; // A5
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adc4.set_resolution(adc4::Resolution::BITS12);
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adc4.set_resolution(adc4::Resolution::BITS12);
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adc4.set_averaging(adc4::Averaging::Samples256);
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adc4.set_averaging(adc4::Averaging::Samples256);
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adc4.set_sample_time(adc4::SampleTime::CYCLES1_5);
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adc4.set_sample_time(adc4::SampleTime::CYCLES1_5);
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let max4 = adc4::resolution_to_max_count(adc4::Resolution::BITS12);
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let max4 = adc4::resolution_to_max_count(adc4::Resolution::BITS12);
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let raw: u16 = adc.blocking_read(&mut adc_pin1);
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// **** ADC1 blocking read ****
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let volt: f32 = 3.3 * raw as f32 / max as f32;
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let raw: u16 = adc1.blocking_read(&mut adc1_pin1);
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info!("Read 1 pin 1 {}", volt);
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let volt: f32 = 3.3 * raw as f32 / max1 as f32;
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info!("Read adc1 pin 1 {}", volt);
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let raw: u16 = adc.blocking_read(&mut adc_pin2);
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let raw: u16 = adc1.blocking_read(&mut adc1_pin2);
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let volt: f32 = 3.3 * raw as f32 / max as f32;
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let volt: f32 = 3.3 * raw as f32 / max1 as f32;
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info!("Read 1 pin 2 {}", volt);
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info!("Read adc1 pin 2 {}", volt);
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let raw4: u16 = adc4.blocking_read(&mut adc4_pin1);
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// **** ADC2 blocking read ****
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let volt4: f32 = 3.3 * raw4 as f32 / max4 as f32;
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let raw: u16 = adc2.blocking_read(&mut adc2_pin1);
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info!("Read 4 pin 1 {}", volt4);
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let volt: f32 = 3.3 * raw as f32 / max2 as f32;
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info!("Read adc2 pin 1 {}", volt);
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let raw4: u16 = adc4.blocking_read(&mut adc4_pin2);
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let raw: u16 = adc2.blocking_read(&mut adc2_pin2);
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let volt4: f32 = 3.3 * raw4 as f32 / max4 as f32;
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let volt: f32 = 3.3 * raw as f32 / max2 as f32;
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info!("Read 4 pin 2 {}", volt4);
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info!("Read adc2 pin 2 {}", volt);
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let mut degraded1 = adc_pin1.degrade_adc();
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// **** ADC4 blocking read ****
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let mut degraded2 = adc_pin2.degrade_adc();
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let raw: u16 = adc4.blocking_read(&mut adc4_pin1);
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let volt: f32 = 3.3 * raw as f32 / max4 as f32;
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info!("Read adc4 pin 1 {}", volt);
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let raw: u16 = adc4.blocking_read(&mut adc4_pin2);
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let volt: f32 = 3.3 * raw as f32 / max4 as f32;
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info!("Read adc4 pin 2 {}", volt);
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// **** ADC1 async read ****
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let mut degraded11 = adc1_pin1.degrade_adc();
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let mut degraded12 = adc1_pin2.degrade_adc();
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let mut measurements = [0u16; 2];
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let mut measurements = [0u16; 2];
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adc.read(
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adc1.read(
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&mut p.GPDMA1_CH0,
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&mut p.GPDMA1_CH0,
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[
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[
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(&mut degraded2, adc::SampleTime::CYCLES160_5),
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(&mut degraded11, adc::SampleTime::CYCLES160_5),
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(&mut degraded1, adc::SampleTime::CYCLES160_5),
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(&mut degraded12, adc::SampleTime::CYCLES160_5),
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]
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]
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.into_iter(),
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.into_iter(),
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&mut measurements,
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&mut measurements,
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).await;
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).await;
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let volt1: f32 = 3.3 * measurements[1] as f32 / max as f32;
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let volt1: f32 = 3.3 * measurements[0] as f32 / max1 as f32;
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let volt2: f32 = 3.3 * measurements[0] as f32 / max as f32;
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let volt2: f32 = 3.3 * measurements[1] as f32 / max1 as f32;
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info!("Async read 1 pin 1 {}", volt1);
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info!("Async read 1 pin 1 {}", volt1);
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info!("Async read 1 pin 2 {}", volt2);
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info!("Async read 1 pin 2 {}", volt2);
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// **** ADC2 does not support async read ****
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// **** ADC4 async read ****
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let mut degraded41 = adc4_pin1.degrade_adc();
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let mut degraded42 = adc4_pin2.degrade_adc();
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let mut measurements = [0u16; 2];
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// The channels must be in ascending order and can't repeat for ADC4
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adc4.read(
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&mut p.GPDMA1_CH1,
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[
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&mut degraded42,
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&mut degraded41,
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]
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.into_iter(),
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&mut measurements,
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).await.unwrap();
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let volt2: f32 = 3.3 * measurements[0] as f32 / max4 as f32;
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let volt1: f32 = 3.3 * measurements[1] as f32 / max4 as f32;
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info!("Async read 4 pin 1 {}", volt1);
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info!("Async read 4 pin 2 {}", volt2);
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}
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}
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