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rcc: enable lse for stm32u0

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This commit is contained in:
Christian Enderle 2024-11-21 19:41:41 +01:00
parent bd65906d14
commit 48fd80919a
1 changed files with 5 additions and 2 deletions
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7
embassy-stm32/src/rcc/bd.rs
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@ -159,6 +159,9 @@ impl LsConfig {
} else {
None
};
#[cfg(rcc_u0)]
let lse_sysen = Some(lse_en);
_ = lse_drv; // not all chips have it.
// Disable backup domain write protection
@ -199,7 +202,7 @@ impl LsConfig {
}
ok &= reg.lseon() == lse_en;
ok &= reg.lsebyp() == lse_byp;
#[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba))]
#[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba, rcc_u0))]
if let Some(lse_sysen) = lse_sysen {
ok &= reg.lsesysen() == lse_sysen;
}
@ -251,7 +254,7 @@ impl LsConfig {
while !bdcr().read().lserdy() {}
#[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba))]
#[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba, rcc_u0))]
if let Some(lse_sysen) = lse_sysen {
bdcr().modify(|w| {
w.set_lsesysen(lse_sysen);